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| MFRC522 Contactless Reader IC Rev. 3.2 -- 22 May 2007 112132 Product data sheet PUBLIC INFORMATION 1. Introduction This document describes the functionality of the contactless reader/writer MFRC522. It includes the functional and electrical specifications. 2. General description The MFRC522 is a highly integrated reader/writer for contactless communication at 13.56 MHz. The MFRC522 reader supports ISO 14443A / MIFARE(R) mode. The MFRC522's internal transmitter part is able to drive a reader/writer antenna designed to communicate with ISO/IEC 14443A/MIFARE(R) cards and transponders without additional active circuitry. The receiver part provides a robust and efficient implementation of a demodulation and decoding circuitry for signals from ISO/IEC 14443A/MIFARE(R) compatible cards and transponders. The digital part handles the complete ISO/IEC 14443A framing and error detection (Parity & CRC).The MFRC522 supports MIFARE(R)Classic (e.g. MIFARE(R) Standard) products. The MFRC522 supports contactless communication using MIFARE(R) higher transfer speeds up to 848 kbit/s in both directions. Various host interfaces are implemented: * SPI interface * serial UART (similar to RS232 with voltage levels according pad voltage supply) * I2C interface. 3. Features Highly integrated analog circuitry to demodulate and decode responses Buffered output drivers to connect an antenna with minimum number of external components Supports ISO/IEC 14443A / MIFARE(R) Typical operating distance in Reader/Writer mode for communication to a ISO/IEC 14443A / MIFARE(R) up to 50 mm depending on the antenna size and tuning Supports MIFARE(R) Classic encryption in Reader/Writer mode Supports ISO/IEC 14443A higher transfer speed communication up to 848 kbit/s Support of the MFIN / MFOUT Additional power supply to directly supply the smart card IC connected via MFIN / MFOUT Supported host interfaces NXP Semiconductors MFRC522 Contactless Reader IC SPI interface up to 10 Mbit/s I2C interface up to 400 kbit/s in Fast mode, up to 3400 kbit/s in High-speed mode serial UART in different transfer speeds up to 1228.8 kbit/s, framing according to the RS232 interface with voltage levels according pad voltage supply Comfortable 64 byte send and receive FIFO-buffer Flexible interrupt modes Hard reset with low power function Power-down mode per software Programmable timer Internal oscillator to connect 27.12 MHz quartz 2.5 - 3.3 V power supply CRC Co-processor Free programmable I/O pins Internal self test 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 2 of 109 NXP Semiconductors MFRC522 Contactless Reader IC 4. Quick reference data Table 1. Symbol AVDD DVDD TVDD PVDD SVDD IHPD ISPD IDVDD IAVDD IAVDD,RCVOFF IPVDD ITVDD Tamb [1] [2] [3] [4] [5] [6] [7] [8] Quick reference data Parameter Supply Voltage Conditions AVSS = DVSS = PVSS= TVSS = 0 V, PVDD AVDD = DVDD =TVDD Pad power supply MFIN/MFOUT Pad Power Supply Hard Power-down Current Soft Power-down Current Digital Supply Current Analog Supply Current Analog Supply Current, receiver switched off Pad Supply Current Transmitter Supply Current operating ambient temperature Continuous Wave AVSS = DVSS = PVSS= TVSS = 0 V, PVDD AVDD = DVDD =TVDD AVSS = DVSS = PVSS= TVSS = 0 V, AVDD = DVDD = TVDD = PVDD = 3 V, NRESET = LOW AVDD = DVDD = TVDD = PVDD = 3 V, RF level detector on DVDD = 3 V AVDD = 3 V, bit RCVOff = 0 AVDD = 3 V, bit RCVOff = 1 [2] [1][3][8] [4] [1][2] [1][2] [1][2] [3] Min 2.5 Typ - Max 3.6 Unit V 1.6 1.6 -25 6.5 7 3 60 3.6 3.6 5 10 9 10 5 40 100 +85 V V A A mA mA mA mA mA C [4] Supply voltage below 3 V reduces the performance (e.g. the achievable operating distance). AVDD, DVDD and TVDD shall always be on the same voltage level. PVDD shall always be on the same or lower voltage level than DVDD. ITVDD depends on TVDD and the external circuitry connected to Tx1 and Tx2 IPVDD depends on the overall load at the digital pins. During operation with a typical circuitry the overall current is below 100 mA. ISPD and IHPD are the total currents over all supplies. Typical value using a complementary driver configuration and an antenna matched to 40 between TX1 and TX2 at 13.56 MHz 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 3 of 109 NXP Semiconductors MFRC522 Contactless Reader IC 5. Ordering information Table 2: Ordering information Package Name MFRC52201HN1/TRAYB (delivered in 1 Tray) MFRC52201HN1/TRAYBM HVQFN32 (delivered in 5 Tray) HVQFN32 Description Version see Package Outline in Figure 33 "Package outline package version SOT617-1 (HVQFN32)" see Packing Information in Figure 34 "Packing Information 1 Tray" see Package Outline in Figure 33 "Package outline package version SOT617-1 (HVQFN32)" see Packing Information in Figure 35 "Packing Information 5Tray" Type number 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 4 of 109 NXP Semiconductors MFRC522 Contactless Reader IC 6. Block diagram The Analog interface handles the modulation and demodulation of the analog signals. The contactless UART handles the protocol requirements for the communication schemes in co-operation with the host. The comfortable FIFO buffer allows a fast and convenient data transfer from the host to the contactless UART and vice versa. Various host interfaces are implemented to fulfil different customer requirements. Registerbank Analog Interface Contactless UART FIFO Serial UART SPI I2C Host Fig 1. Simplified MFRC522 Block diagram 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 5 of 109 NXP Semiconductors MFRC522 Contactless Reader IC SDA EA, I2C D1 to D7 PVDD PVSS DVDD SPI, UART, I2C Interface Control Voltage Monitor & Power On Detect State Machine Reset Control DVSS AVDD AVSS FIFO Control Command Register 64 Byte FIFO Programable Timer Power Down Control NRSTPD Control Register Bank Interrupt Control IRQ CRC16 Generation & Check MIFARE Classic Unit Parallel/Seriell Converter Random Number Generator Bit Counter Parity Generation & Check Frame Generation & Check Bit Decoding Bit Coding MFIN Serial Data Switch MFOUT SVDD Amplitude Rating A/D Converter Reference Voltage Clock Generation, Filtering and Distribution OSCIN Oscillator OSCOUT Q-Clock Generation Analog Test MUX and DAC I-Channel Amplifier I-Channel Demodulator Q-Channel Amplifier Q-Channel Demodulator Temperature Sensor Transmitter Control G ND V+ G ND V+ VMID AUX1,2 RX TVSS TX1 TX2 TVDD Fig 2. MFRC522 Block diagram 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 6 of 109 NXP Semiconductors MFRC522 Contactless Reader IC 7. Pinning information 7.1 Pinning Fig 3. Pinning configuration HVQFN32 (SOT617-1). 7.2 Pin description Table 3: Symbol I2 C PVDD DVDD DVSS PVSS NRSTPD 1 2 3 4 5 6 Pin description Pin Type I PWR PWR PWR PWR I Description I2C enable[2] Pad power supply Digital Power Supply Digital Ground[1] Pad power supply ground Not Reset and Power-down: When LOW, internal current sinks are switched off, the oscillator is inhibited, and the input pads are disconnected from the outside world. With a positive edge on this pin the internal reset phase starts. Mifare Signal Input Mifare Signal Output MFIN / MFOUT Pad Power Supply: provides power to for the MFIN / MFOUT pads Transmitter Ground: supplies the output stage of TX1 and TX2 (c) NXP B.V. 2007. All rights reserved. MFIN MFOUT SVDD TVSS 112132 7 8 9 10, 14 I O PWR PWR Product data sheet Rev. 3.2 -- 22 May 2007 7 of 109 NXP Semiconductors MFRC522 Contactless Reader IC Pin description ...continued Pin 11 12 13 10, 14 15 16 17 18 19 20 21 Type O PWR O PWR PWR PWR I PWR O O I Crystal Oscillator Input: input to the inverting amplifier of the oscillator. This pin is also the input for an externally generated clock (fosc = 27.12 MHz). Crystal Oscillator Output: Output of the inverting amplifier of the oscillator. Interrupt Request: output to signal an interrupt event Serial Data Line[2] Data Pins for different interfaces (test port, I2IC, SPI, UART)[2] Description Transmitter 1: delivers the modulated 13.56 MHz energy carrier Transmitter Power Supply: supplies the output stage of TX1 and TX2 Transmitter 2: delivers the modulated 13.56 MHz energy carrier Transmitter Ground: supplies the output stage of TX1 and TX2 Analog Power Supply Internal Reference Voltage: This pin delivers the internal reference voltage. Receiver Input. Pin for the received RF signal. Analog Ground Auxiliary Outputs: These pins are used for testing. Table 3: Symbol TX1 TVDD TX2 TVSS AVDD VMID RX AVSS AUX1 AUX2 OSCIN OSCOUT IRQ SDA D1 D2 D3 D4 D5 D6 D7 EA [1] [2] 22 23 24 25 26 27 28 29 30 31 32 O O I I/O I/O I/O I/O I/O I/O I/O I External Address: This Pin is used for coding I2C Address[2] Connection of heat sink pad on package buttom side is not necessary. Optional connection to DVSS is possible. The pin functionality for the interfaces is explained in Section 10 "DIGITAL Interfaces". 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 8 of 109 NXP Semiconductors MFRC522 Contactless Reader IC 8. Functional description MFRC522 transmission module supports the Reader/Writer mode for ISO/IEC 14443A/MIFARE(R) with different transfer speeds and modulation schemes. Battery RC522 ISO 14443A Card C Reader/Writer Fig 4. MFRC522 Reader/Writer mode. Contactless Card The following diagram Figure 5 "ISO/IEC 14443A/MIFARE(R) Reader/Writer mode communication diagram." describes the communication on a physical level. ISO14443A Reader RC522 1. Reader to Card 100 % ASK , Miller Coded, Transfer speed 106 to 848 kbit/s ISO14443A Card 2. Card to Reader, Subcarrier Loadmodulation , Manchester Coded or BPSK, Transfer speed 106 to 848 kbit/s Fig 5. ISO/IEC 14443A/MIFARE(R) Reader/Writer mode communication diagram. The communication overview in Table 4 "Communication overview for ISO/IEC 14443A/MIFARE(R) reader/writer" describes the physical parameters. Table 4: Communication overview for ISO/IEC 14443A/MIFARE(R) reader/writer ISO/IEC 14443A/ MIFARE(R) transfer speed Modulation on reader side bit coding Bitlength 106 kbit/s 100% ASK 212 kbit/s 100% ASK 424 kbit/s 100% ASK 848 kbit/s 100% ASK Communication direction Reader Card (send data from the MFRC522 to a card) Modified Miller Modified coding Miller coding Modified Miller coding Modified Miller coding (128/13.56) s (64/13.56) s (32/13.56) s (16/13.56) s 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 9 of 109 NXP Semiconductors MFRC522 Contactless Reader IC Communication overview for ISO/IEC 14443A/MIFARE(R) reader/writer ...continued ISO/IEC 14443A/ MIFARE(R) transfer speed modulation on card side subcarrier frequency bit coding 106 kbit/s subcarrier load modulation 13.56 MHz/16 Manchester coding 212 kbit/s subcarrier load modulation 424 kbit/s subcarrier load modulation 848 kbit/s subcarrier load modulation Table 4: Communication direction Card Reader (MFRC522 receives data from a card) 13.56MHz/16 13.56MHz/16 13.56MHz/16 BPSK BPSK BPSK The contactless UART of MFRC522 and a dedicated external host are required to handle the complete MIFARE(R) / ISO/IEC 14443A / MIFARE(R) protocol. The following Figure 6 "Data Coding and framing according to ISO/IEC 14443A." shows the Data Coding and framing according to ISO/IEC 14443A / MIFARE(R). ISO14443-A Framing at 106 kbit/s Start 8 bit data Start Bit is "1" odd Par 8 bit data odd Par 8 bit data odd Par ISO14443-A Framing at 212, 424 and 848 kbit/s Start 8 bit data Burst of 32 subcarrier clocks Fig 6. 8 bit data odd Par odd Par 8 bit data Even parity at the end of the frame! even Par. Start Bit is "0" Data Coding and framing according to ISO/IEC 14443A. The internal CRC co-processor calculates the CRC value according to the definitions given in the ISO/IEC 14443A part 3 and handles parity generation internally according to the transfer speed. Automatic parity generation can be switched off by bit ParityDisable in register 0x1D ManualRCVReg. 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 10 of 109 NXP Semiconductors MFRC522 Contactless Reader IC 9. MFRC522 Register SET 9.1 MFRC522 Registers Overview Table 5: Addr (hex) 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 112132 MFRC522 Registers Overview Register Name Function Page 0: Command and Status Reserved CommandReg ComlEnReg DivlEnReg ComIrqReg DivIrqReg ErrorReg Status1Reg Status2Reg FIFODataReg FIFOLevelReg WaterLevelReg ControlReg BitFramingReg CollReg Reserved Reserved ModeReg TxModeReg RxModeReg TxControlReg TxASKReg TxSelReg RxSelReg DemodReg Reserved Reserved MfTxReg MfRxReg Reserved SerialSpeedReg Reserved Reserved for future use Starts and stops command execution Controls bits to enable and disable the passing of Interrupt Requests Controls bits to enable and disable the passing of Interrupt Requests Contains Interrupt Request bits Contains Interrupt Request bits Error bits showing the error status of the last command executed Contains status bits for communication Contains status bits of the receiver and transmitter In- and output of 64 byte FIFO buffer Indicates the number of bytes stored in the FIFO Defines the level for FIFO under- and overflow warning Contains miscellaneous Control Registers Adjustments for bit oriented frames Bit position of the first bit collision detected on the RF-interface Reserved for future use Reserved for future use Defines general modes for transmitting and receiving Defines the transmission data rate and framing Defines the receive data rate and framing Controls the logical behavior of the antenna driver pins TX1 and TX2 Controls the setting of the TX modulation Selects the internal sources for the antenna driver Selects internal receiver settings Defines demodulator settings Reserved for future use Reserved for future use Controls some MIFARE(R) communication transmit parameters Controls some MIFARE(R) communication receive parameters Reserved for future use Selects the speed of the serial UART interface Reserved for future use (c) NXP B.V. 2007. All rights reserved. Page 1: Command RxThresholdReg Selects thresholds for the bit decoder Page 2: CFG Product data sheet Rev. 3.2 -- 22 May 2007 11 of 109 NXP Semiconductors MFRC522 Contactless Reader IC MFRC522 Registers Overview ...continued Register Name CRCResultReg Reserved ModWidthReg Reserved RFCfgReg GsNReg CWGsPReg ModGsPReg TModeReg TPrescalerReg TReloadReg Defines settings for the internal timer Describes the 16 bit timer reload value Function Shows the actual MSB and LSB values of the CRC calculation Reserved for future use Controls the setting of the ModWidth Reserved for future use Configures the receiver gain Selects the conductance of the antenna driver pins TX1 and TX2 for modulation Table 5: Addr (hex) 1 2 3 4 5 6 7 8 9 A B C D E F TCounterValReg Shows the 16 bit actual timer value Page 3: TestRegister 0 1 2 3 4 5 6 7 8 9 A B C-F Reserved TestSel1Reg TestSel2Reg TestPinEnReg TestBusReg AutoTestReg VersionReg AnalogTestReg TestDAC1Reg TestDAC2Reg TestADCReg Reserved Reserved for future use General test signal configuration General test signal configuration and PRBS control Enables pin output driver on D1-D7 Shows the status of the internal testbus Controls the digital selftest Shows the version Controls the pins AUX1 and AUX2 Defines the test value for the TestDAC1 Defines the test value for the TestDAC2 Shows the actual value of ADC I and Q Reserved for production tests TestPinValueReg Defines the values for D1 - D7 when it is used as I/O bus 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 12 of 109 NXP Semiconductors MFRC522 Contactless Reader IC 9.1.1 Register Bit Behavior Depending on the functionality of a register, the access conditions to the register can vary. In principle bits with same behavior are grouped in common registers. In Table 6 the access conditions are described. Table 6: r/w Behavior of Register Bits and its Designation Description read and write These bits can be written and read by the -Controller. Since they are used only for control means, there content is not influenced by internal state machines, e.g. the ComIEnReg-Register may be written and read by the -Controller. It will also be read by internal state machines, but never changed by them. dynamic These bits can be written and read by the -Controller. Nevertheless, they may also be written automatically by internal state machines, e.g. the Command-Register changes its value automatically after the execution of the actual command. These register bits hold values which are determined by internal states only, e.g. the CRCReady bit can not be written from external but shows internal states. Reading these register bits returns always ZERO. These registers are reserved for future use and shall not be changed. In case of a write access, it is recommended to write always the value "0". These register bits are reserved for future use or production test and shall not be changed. Abbreviation Behavior dy r read only w RFU write only - RFT - 9.2 Register Description 9.2.1 Page 0: Command and Status 9.2.1.1 Reserved Functionality is reserved for further use. Table 7: Bit Symbol Access Rights Table 8: Bit 7 to 0 Description of Reserved register bits Symbol Description Reserved for future use. Reserved register (address 00h); reset value: 00h 7 6 5 4 RFU 3 2 1 0 9.2.1.2 CommandReg Starts and stops command execution. 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 13 of 109 NXP Semiconductors MFRC522 Contactless Reader IC CommandReg register (address 01h); reset value: 20h 7 RFU 6 5 RcvOff r/w 4 Power Down dy 3 2 dy 1 0 Command Table 9: Bit Symbol Access Rights Table 10: Bit 7 to 6 5 4 Description of CommandReg bits Symbol RcvOff PowerDown Description Reserved for future use. Set to logic 1, the analog part of the receiver is switched off. Set to logic 1, Soft Power-down mode is entered. Set to logic 0, the MFRC522 starts the wake up procedure. During this procedure this bit still shows a logic 1. A logic 0 indicates that the MFRC522 is ready for operations; see Section 16.2 "Soft Power-down". Remark: The bit PowerDown cannot be set, when the command SoftReset has been activated. 3 to 0 Command Activates a command according to the Command Code. Reading this register shows which command is actually executed (see Section 18.3 "MFRC522 Commands Overview"). 9.2.1.3 CommIEnReg Control bits to enable and disable the passing of interrupt requests. Table 11: Bit Symbol Access Rights Table 12: Bit 7 CommIEnReg register (address 02h); reset value: 80h 7 IRqInv r/w 6 TxIEn r/w 5 RxIEn r/w 4 IdleIEn r/w 3 HiAlertIEn r/w 2 LoAlertIEn r/w 1 ErrIEn r/w 0 TimerIEn r/w Description of CommIEnReg bits Description Set to logic 1, the signal on pin IRQ is inverted with respect to bit IRq in the register Status1Reg. Set to logic 0, the signal on pin IRQ is equal to bit IRq. In combination with bit IRqPushPull in register DivIEnReg, the default value of logic 1 ensures, that the output level on pin IRQ is tristate. Allows the transmitter interrupt request (indicated by bit TxIRq) to be propagated to pin IRQ. Allows the receiver interrupt request (indicated by bit RxIRq) to be propagated to pin IRQ. Allows the idle interrupt request (indicated by bit IdleIRq) to be propagated to pin IRQ. Allows the high alert interrupt request (indicated by bit HiAlertIRq) to be propagated to pin IRQ. Symbol IRqInv 6 5 4 3 TxIEn RxIEn IdleIEn HiAlertIEn 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 14 of 109 NXP Semiconductors MFRC522 Contactless Reader IC Description of CommIEnReg bits Description Allows the low alert interrupt request (indicated by bit LoAlertIRq) to be propagated to pin IRQ. Allows the error interrupt request (indicated by bit ErrIRq) to be propagated to pin IRQ. Allows the timer interrupt request (indicated by bit TimerIRq) to be propagated to pin IRQ. Table 12: Bit 2 1 0 Symbol LoAlertIEn ErrIEn TimerIEn 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 15 of 109 NXP Semiconductors MFRC522 Contactless Reader IC 9.2.1.4 DivIEnReg Control bits to enable and disable the passing of interrupt requests. Table 13: Bit Access Rights Table 14: Bit 7 6 to 5 4 3 2 1 to 0 DivIEnReg register (address 03h); reset value: 00h 7 r/w 6 RFU 5 4 MfinActIEn r/w 3 RFU 2 CRCIEn r/w 1 RFU 0 Symbol IRQPushPull Description of DivIEnReg bits Symbol IRQPushPull MfinActIEn CRCIEn Description Set to logic 1, the pin IRQ works as standard CMOS output pad. Set to logic 0, the pin IRQ works as open drain output pad. Reserved for future use. Allows the MFIN active interrupt request to be propagated to pin IRQ. Reserved for future use. Allows the CRC interrupt request (indicated by bit CRCIRq) to be propagated to pin IRQ. Reserved for future use. 9.2.1.5 CommIRqReg Contains Interrupt Request bits. Table 15: Bit Symbol Access Rights CommIRqReg register (address 04h); reset value: 14h 7 Set1 w 6 TxIRq dy 5 RxIRq dy 4 IdleIRq dy 3 dy 2 dy 1 ErrIRq dy 0 TimerIRq dy HiAlertIRq LoAlertIRq Table 16: Description of CommIRqReg bits All bits in the register CommIRqReg shall be cleared by software. Bit 7 Symbol Set1 Description Set to logic 1, Set1 defines that the marked bits in the register CommIRqReg are set. Set to logic 0, Set1 defines, that the marked bits in the register CommIRqReg are cleared. 6 5 TxIRq RxIRq Set to logic 1 immediately after the last bit of the transmitted data was sent out. Set to logic 1 when the receiver detects the end of a valid data stream. If the bit RxNoErr in register RxModeReg is set to logic 1, Bit RxIRq is only set to logic 1 when data bytes are available in the FIFO. 4 IdleIRq Set to logic 1, when a command terminates by itself e.g. when the CommandReg changes its value from any command to the Idle Command. If an unknown command is started, the CommandReg changes its content to the idle state and the bit IdleIRq is set. Starting the Idle Command by the -Controller does not set bit IdleIRq. 3 HiAlertIRq Set to logic 1, when bit HiAlert in register Status1Reg is set. In opposition to HiAlert, HiAlertIRq stores this event and can only be reset as indicated by bit Set1. (c) NXP B.V. 2007. All rights reserved. 112132 Product data sheet Rev. 3.2 -- 22 May 2007 16 of 109 NXP Semiconductors MFRC522 Contactless Reader IC Table 16: Description of CommIRqReg bits ...continued All bits in the register CommIRqReg shall be cleared by software. Bit 2 Symbol Description LoAlertIRq Set to logic 1, when bit LoAlert in register Status1Reg is set. In opposition to LoAlert, LoAlertIRq stores this event and can only be reset as indicated by bit Set1. ErrIRq TimerIRq Set to logic 1 if any error bit in the ErrorReg Register is set. Set to logic 1 when the timer decrements the TimerValue Register to zero. 1 0 9.2.1.6 DivIRqReg Contains Interrupt Request bits Table 17: Bit Symbol Access Rights DivIRqReg register (address 05h); reset value: X0h 7 Set2 w 6 RFU 5 4 MfinActIRq dy 3 RFU 2 CRCIRq dy 1 RFU 0 Table 18: Description of DivIRqReg bits All bits in the register DivIRqReg shall be cleared by software. Bit 7 Symbol Set2 Description Set to logic 1, Set2 defines that the marked bits in the register DivIRqReg are set. Set to logic 0, Set2 defines, that the marked bits in the register DivIRqReg are cleared 6 to 5 4 3 2 1 to 0 MfinActIRq CRCIRq Reserved for future use. Set to logic 1, when MFIN is active. This interrupt is set when either a rising or falling signal edge is detected. Reserved for future use. Set to logic 1, when the CRC command is active and all data are processed. Reserved for future use. 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 17 of 109 NXP Semiconductors MFRC522 Contactless Reader IC 9.2.1.7 ErrorReg Error bit register showing the error status of the last command executed. Table 19: Bit Symbol Access Rights Table 20: Bit 7 ErrorReg register (address 06h); reset value: 00h 7 WrErr r 6 TempErr r 5 RFU 4 BufferOvfl r 3 CollErr r 2 CRCErr r 1 ParityErr r 0 ProtocolErr r Description of ErrorReg bits Symbol WrErr Description Set to logic 1, when data is written into the FIFO by the host during the MFAuthent command or if data is written into the FIFO by the host during the time between sending the last bit on the RF interface and receiving the last bit on the RF interface. Set to logic 1, if the internal temperature sensor detects overheating. In this case, the antenna drivers are switched off automatically. Reserved for future use. Set to logic 1, if the host or a MFRC522's internal state machine (e.g. receiver) tries to write data into the FIFO buffer although the FIFO buffer is already full. Set to logic 1, if a bit-collision is detected. It is cleared automatically at receiver start-up phase. This bit is only valid during the bitwise anticollision at 106 kbit/s. During communication schemes at 212, 424 and 848 kbit/s this bit is always set to logic 0. Set to logic 1, if bit RxCRCEn in register RxModeReg is set and the CRC calculation fails. It is cleared to logic 0 automatically at receiver start-up phase. Set to logic 1, if the parity check has failed. It is cleared automatically at receiver start-up phase. Only valid for ISO/IEC 14443A/MIFARE(R) communication at 106 kbit/s. Set to logic 1, if one out of the following cases occur: 6 5 4 TempErr[1] BufferOvfl 3 CollErr 2 CRCErr 1 ParityErr 0 ProtocolErr * * [1] Set to logic 1 if the SOF is incorrect. It is cleared automatically at receiver start-up phase. The bit is only valid for 106 kbit/s. During the MFAuthent Command, bit ProtocolErr is set to logic 1, if the number of bytes received in one data stream is incorrect. Command execution will clear all error bits except for bit TempErr. A setting by software is impossible. 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 18 of 109 NXP Semiconductors MFRC522 Contactless Reader IC 9.2.1.8 Status1Reg Contains status bits of the CRC, Interrupt and FIFO buffer. Table 21: Bit Symbol Access Rights Table 22: Bit 7 6 Status1Reg register (address 07h); reset value: 21h 7 RFU 6 r 5 r 4 IRq r 3 TRunning r 2 RFU 1 HiAlert r 0 LoAlert r CRCOk CRCReady Description of Status1Reg bits Symbol CRCOk Description Reserved for future use. Set to logic 1, if the CRC result is zero. For data transmission and reception the bit CRCOk is undefined (use CRCErr in register ErrorReg). CRCOk indicates the status of the CRC co-processor, during calculation the value changes to logic 0, when the calculation is done correctly, the value changes to logic 1. Set to logic 1, when the CRC calculation has finished. This bit is only valid for the CRC co-processor calculation using the command CalcCRC. This bit shows, if any interrupt source requests attention (with respect to the setting of the interrupt enable bits, see register CommIEnReg and DivIEnReg). Set to logic 1, if the MFRC522's timer unit is running, e.g. the timer will decrement the TCounterValReg with the next timer clock. Remark: In the gated mode the bit TRunning is set to logic 1, when the timer is enabled by the register bits. This bit is not influenced by the gated signal. 5 CRCReady 4 IRq 3 TRunning 2 1 HiAlert Reserved for future use. Set to logic 1, when the number of bytes stored in the FIFO buffer fulfils the following equation: HiAlert = ( 64 - FIFOLength ) WaterLevel Example: FIFOLength = 60, WaterLevel = 4 HiAlert = 1 FIFOLength = 59, WaterLevel = 4 HiAlert = 0 0 LoAlert Set to logic 1, when the number of bytes stored in the FIFO buffer fulfils the following equation: LoAlert = FIFOLength WaterLevel Example: FIFOLength = 4, WaterLevel = 4 LoAlert = 1 FIFOLength = 5, WaterLevel = 4 LoAlert = 0 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 19 of 109 NXP Semiconductors MFRC522 Contactless Reader IC 9.2.1.9 Status2Reg Contains status bits of the receiver, transmitter and data mode detector. Table 23: Bit Symbol Access Rights Table 24: Bit 7 6 Status2Reg register (address 08h); reset value: 00h 7 TempSens Clear r/w 6 I2CForceHS r/w 5 RFU 4 3 MFCrypto1On dy 2 1 Modem State r 0 Description of Status2Reg bits Symbol TempSensClear I2CForceHS Description Set to logic 1, this bit clears the temperature error, if the temperature is below the alarm limit of 125 C. I2C input filter settings. Set to logic 1, the I2C input filter is set to the High-speed mode independent of the I2C protocol. Set to logic 0, the I2C input filter is set to the used I2C protocol. Reserved for future use. This bit indicates that the MIFARE(R) Crypto1 unit is switched on and therefore all data communication with the card is encrypted. This bit can only be set to logic 1 by a successful execution of the MFAuthent Command. This bit is only valid in Reader/Writer mode for MIFARE(R) Standard cards. This bit shall be cleared by software. 5 to 4 3 MFCrypto1On 2 to 0 Modem State ModemState shows the state of the transmitter and receiver state machines. Status Description 000 001 010 IDLE Wait for bit StartSend in register BitFramingReg TxWait: Wait until Rf field is present, if the bit TxWaitRF is set to logic 1. The minimum time for TxWait is defined by the TxWaitReg register. Transmitting RxWait: Wait until RF field is present, if the bit RxWaitRF is set to logic 1. The minimum time for RxWait is defined by the RxWaitReg register. Wait for data Receiving 011 100 101 110 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 20 of 109 NXP Semiconductors MFRC522 Contactless Reader IC 9.2.1.10 FIFODataReg In- and output of 64 byte FIFO buffer. Table 25: Bit Symbol Access Rights Table 26: Bit 7 to 0 Description ofFIFODataReg bits Symbol FIFOData Description Data input and output port for the internal 64 byte FIFO buffer. The FIFO buffer acts as parallel in/parallel out converter for all serial data stream in- and outputs. FIFODataReg register (address 09h); reset value: XXh 7 6 5 4 FIFOData dy 3 2 1 0 9.2.1.11 FIFOLevelReg Indicates the number of bytes stored in the FIFO. Table 27: Bit Symbol Access Rights Table 28: Bit 7 FIFOLevelReg register (address 0Ah); reset value: 00h 7 FlushBuffer w 6 5 4 3 FIFOLevel r 2 1 0 Description of FIFOLevelReg bits Symbol FlushBuffer Description Set to logic 1, this bit clears the internal FIFO-buffer's read- and write-pointer and the bit BufferOvfl in the register ErrReg immediately. Reading this bit will always return 0. Indicates the number of bytes stored in the FIFO buffer. Writing to the FIFODataReg increments, reading decrements the FIFOLevel. 6 to 0 FIFOLevel 9.2.1.12 WaterLevelReg Defines the level for FIFO under- and overflow warning. Table 29: Bit Symbol Access Rights WaterLevelReg register (address 0Bh); reset value: 08h 7 RFU 6 5 4 3 r/w 2 1 0 WaterLevel 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 21 of 109 NXP Semiconductors MFRC522 Contactless Reader IC Description of WaterLevelReg bits Symbol WaterLevel Description Reserved for future use. This register defines a warning level to indicate a FIFO-buffer over- or underflow: The bit HiAlert in Status1Reg is set to logic 1, if the remaining number of bytes in the FIFO-buffer space is equal or less than the defined number of WaterLevel bytes. The bit LoAlert in Status1Reg is set to logic 1, if equal or less than WaterLevel bytes are in the FIFO. Remark: For the calculation of HiAlert and LoAlert see Section 9.2.1.8 "Status1Reg". Table 30: Bit 7 to 6 5 to 0 9.2.1.13 ControlReg Miscellaneous control bits. Table 31: Bit Symbol Access Rights Table 32: Bit 7 6 5 to 3 2 to 0 ControlReg register (address 0Ch); reset value: 10h 7 w 6 w 5 4 RFU 3 2 1 RxLastBits r 0 TStopNow TStartNow Description of ControlReg bits Description Set to logic 1, the timer stops immediately. Reading this bit will always return 0. Set to logic 1 starts the timer immediately. Reading this bit will always return 0. Reserved for future use. Shows the number of valid bits in the last received byte. If 0, the whole byte is valid. Symbol TStopNow TStartNow RxLastBits 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 22 of 109 NXP Semiconductors MFRC522 Contactless Reader IC 9.2.1.14 BitFramingReg Adjustments for bit oriented frames. Table 33: Bit Symbol Access Rights Table 34: Bit 7 6 to 4 BitFramingReg register (address 0Dh); reset value: 00h 7 StartSend w 6 5 RxAlign r/w 4 3 RFU 2 1 TxLastBits r/w 0 Description of BitFramingReg bits Symbol StartSend RxAlign Description Set to logic 1, the transmission of data starts. This bit is only valid in combination with the Transceive command. Used for reception of bit oriented frames: RxAlign defines the bit position for the first bit received to be stored in the FIFO. Further received bits are stored at the following bit positions. Example: RxAlign = 0: RxAlign = 1: RxAlign = 7: the LSB of the received bit is stored at bit 0, the second received bit is stored at bit position 1. the LSB of the received bit is stored at bit 1, the second received bit is stored at bit position 2. the LSB of the received bit is stored at bit 7, the second received bit is stored in the following byte at bit position 0. This bits shall only be used for bitwise anticollision at 106 kbit/s. In all other modes it shall be set to 0. 3 2 to 0 TxLastBits Reserved for future use. Used for transmission of bit oriented frames: TxLastBits defines the number of bits of the last byte that shall be transmitted. A 000b indicates that all bits of the last byte shall be transmitted. 9.2.1.15 CollReg Defines the first bit collision detected on the RF interface. Table 35: Bit Symbol Access Rights Table 36: Bit 7 CollReg register (address 0Eh); reset value: XXh 7 Values AfterColl r/w 6 RFU 5 CollPos NotValid r 4 3 2 CollPos r 1 0 Description of CollReg bits Symbol ValuesAfterColl Description If this bit is set to logic 0, all receiving bits will be cleared after a collision. This bit shall only be used during bitwise anticollision at 106 kbit/s, otherwise it shall be set to logic 1. Reserved for future use. Set to logic 1, if no collision is detected or the position of the collision is out of the range of bits CollPos. (c) NXP B.V. 2007. All rights reserved. 6 5 CollPosNotValid 112132 Product data sheet Rev. 3.2 -- 22 May 2007 23 of 109 NXP Semiconductors MFRC522 Contactless Reader IC Description of CollReg bits Symbol CollPos Description These bits show the bit position of the first detected collision in a received frame. Only data bits are interpreted. Example: 00h 01h 08h indicates a bit collision in the 32nd bit indicates a bit collision in the 1st bit indicates a bit collision in the 8th bit Table 36: Bit 4 to 0 These bits shall only be interpreted if bit CollPosNotValid is set to logic 0. 9.2.1.16 Reserved Functionality is reserved for further use. Table 37: Bit Symbol Access Rights Table 38: Bit 7 to 0 Description of Reserved register bits Symbol Description Reserved for future use. Reserved register (address 0Fh); reset value: 00h 7 6 5 4 RFU 3 2 1 0 9.2.2 Page 1: Communication 9.2.2.1 Reserved Functionality is reserved for further use. Table 39: Bit Symbol Access Rights Table 40: Bit 7 to 0 Description of Reserved register bits Symbol Description Reserved for future use. Reserved register (address 10h); reset value: 00h 7 6 5 4 RFU 3 2 1 0 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 24 of 109 NXP Semiconductors MFRC522 Contactless Reader IC 9.2.2.2 ModeReg Defines general mode settings for transmitting and receiving. Table 41: Bit Symbol Access Rights Table 42: Bit 7 ModeReg register (address 11h); reset value: 3Fh 7 MSBFirst r/w 6 RFU 5 TxWaitRF r/w 4 RFU 3 PolMFin r/w 2 RFU 1 r/w 0 CRCPreset Description of ModeReg bits Symbol MSBFirst Description Set to logic 1, the CRC co-processor calculates the CRC with MSB first and the CRCResultMSB and the CRCResultLSB in the CRCResultReg register are bit reversed. Remark: During RF communication this bit is ignored. Reserved for future use. Set to logic 1 the transmitter can only be started, if an RF field is generated. Reserved for future use. PolMFin defines the polarity of the MFIN pin. Set to logic 1, the polarity of MFIN pin is active high. Set to logic 0 the polarity of MFIN pin is active low. Remark: The internal envelope signal is coded active low. Changing this bit will generate a MFinActIRq event. 6 5 4 3 TxWaitRF PolMFin 2 1 to 0 CRCPreset Reserved for future use. Defines the preset value for the CRC co-processor for the command CalCRC. Remark: During any communication, the preset values is selected automatically according to the definition in the bits in RxModeReg and TxModeReg. Value 00 01 10 11 Description 0000 6363 A671 FFFF 9.2.2.3 TxModeReg Defines the data rate during transmission. Table 43: Bit Symbol Access Rights TxModeReg register (address 12h); reset value: 00h 7 TxCRCEn r/w 6 5 TxSpeed dy 4 3 InvMod r/w 2 1 RFU 0 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 25 of 109 NXP Semiconductors MFRC522 Contactless Reader IC Description of TxModeReg bits Symbol TxCRCEn Description Set to logic 1, this bit enables the CRC generation during data transmission. Remark: This bit shall only be set to logic 0 at 106 kbit/s. Defines the bit rate while data transmission. The MFRC522 handels transfer speeds up to 848 kbit/s. Value 000 001 010 011 100 101 110 111 Description 106 kbit/s 212 kbit/s 424 kbit/s 848 kbit/s Reserved Reserved Reserved Reserved Table 44: Bit 7 6 to 4 TxSpeed 3 2 to 0 InvMod - Set to logic 1, the modulation for transmitting data is inverted. Reserved for future use. 9.2.2.4 RxModeReg Defines the data rate during reception. Table 45: Bit Symbol Access Rights Table 46: Bit 7 6 to 4 RxModeReg register (address 13h); reset value: 00h 7 RxCRCEn r/w 6 5 RxSpeed dy 4 3 RxNoErr r/w 2 RxMultiple r/w 1 RFU 0 Description of RxModeReg bits Symbol RxCRCEn RxSpeed Description Set to logic 1, this bit enables the CRC calculation during reception. Remark: This bit shall only be set to logic 0 at 106 kbit/s. Defines the bit rate while data receiving. The MFRC522 handles transfer speeds up to 848kbit/s. Value 000 001 010 011 100 101 110 111 Description 106 kbit/s 212 kbit/s 424 kbit/s 848 kbit/s Reserved Reserved Reserved Reserved 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 26 of 109 NXP Semiconductors MFRC522 Contactless Reader IC Description of RxModeReg bits ...continued Symbol RxNoErr RxMultiple Description If set to logic 1, a not valid received data stream (less than 4 bits received) will be ignored. The receiver will remain active. Set to logic 0, the receiver is deactivated after receiving a data frame. Set to logic 1, it is possible to receive more than one data frame. This bit is only valid for data rates above 106 kbit/s to handle the Polling command. Having set this bit, the receive and transceive commands will not terminate automatically. In this case the multiple receiving can only be deactivated by writing any command (except the Receive command) to the CommandReg register or by clearing the bit by the host. If set to logic 1, at the end of a received data stream an error byte is added to the FIFO. The error byte is a copy of the ErrorReg register. Table 46: Bit 3 2 1 to 0 - Reserved for future use. 9.2.2.5 TxControlReg Controls the logical behavior of the antenna driver pins Tx1 and Tx2. Table 47: Bit Symbol Access Rights Table 48: Bit 7 6 5 4 3 TxControlReg register (address 14h); reset value: 80h 7 6 5 4 3 2 RFU 1 0 InvTx2RF InvTx1RF InvTx2RF InvTx1RF Tx2CW On On Off Off r/w r/w r/w r/w r/w Tx2RFEn Tx1RFEn r/w r/w Description of TxControlReg bits Symbol InvTx2RFOn InvTx1RFOn InvTx2RFOff InvTx1RFOff Tx2CW Description Set to logic 1, the output signal at pin TX2 will be inverted, if driver TX2 is enabled. Set to logic 1, the output signal at pin TX1 will be inverted, if driver TX1 is enabled. Set to logic 1, the output signal at pin TX2 will be inverted, if driver TX2 is disabled. Set to logic 1, the output signal at pin TX1 will be inverted, if driver TX1 is disabled. Set to logic 1, the output signal on pin TX2 will deliver continuously the un-modulated 13.56 MHz energy carrier. Set to logic 0, Tx2CW is enabled to modulate the 13.56 MHz energy carrier. 2 1 0 Tx2RFEn Tx1RFEn Reserved for future use. Set to logic 1, the output signal on pin TX2 will deliver the 13.56 MHz energy carrier modulated by the transmission data. Set to logic 1, the output signal on pin TX1 will deliver the 13.56 MHz energy carrier modulated by the transmission data. 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 27 of 109 NXP Semiconductors MFRC522 Contactless Reader IC 9.2.2.6 TxASKReg Controls the settings of the transmit modulation. Table 49: Bit Symbol Access Rights Table 50: Bit 7 6 5 to 0 TxAutoReg register (address 15h); reset value: 00h 7 RFU 6 Force100ASK r/w 5 4 3 RFU 2 1 0 Description of TxAutoReg bits Symbol Force100ASK Description Reserved for future use. Set to logic 1, Force100ASK forces a 100% ASK modulation independent of the setting in register ModGsPReg. Reserved for future use. 9.2.2.7 TxSelReg Selects the internal sources for the analog part. Table 51: Bit Symbol Access Rights Table 52: Bit 7 to 6 5 to 4 DriverSel TxSelReg register (address 16h); reset value: 10h 7 RFU 6 5 DriverSel r/w 4 3 2 MfOutSel r/w 1 0 Description of TxSelReg bits Description Reserved for future use. Selects the input of driver Tx1 and Tx2. Value 00 Description Tristate Remark: In soft power-down the drivers are only in tristate mode if DriverSel is set to tristate mode. 01 10 11 Modulation signal (envelope) from the internal coder, Miller Pulse Coded. Modulation signal (envelope) from MIFIN High Remark: The High level depends on the setting of InvTx1RFOn/ InvTx1RFOff and InvTx2RFOn/ InvTx2RFOff. Symbol 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 28 of 109 NXP Semiconductors MFRC522 Contactless Reader IC Description of TxSelReg bits Description Selects the input for the MFOUT Pin. Value 0000 0001 0010 0011 0100 0101 0110 0111 1000-1111 Description Tristate Low High TestBus signal as defined by bit TestBusBitSel in register TestSel1Reg. Modulation signal (envelope) from the internal coder, Miller Puls Coded Serial data stream to be transmitted, data stream before Miller Coder Reserved Serial data stream received, data stream after Manchester Decoder Reserved Table 52: Bit 3 to 0 Symbol MFOutSel 9.2.2.8 RxSelReg Selects internal receiver settings. Table 53: Bit Symbol Access Rights Table 54: Bit 7 to 6 RxSelReg register (address 17h); reset value: 84h 7 UartSel r/w 6 5 4 3 RxWait r/w 2 1 0 Description of RxSelReg bits Symbol UartSel Description Selects the input of the contactless UART Value 00 01 10 11 Description Constant Low Manchester with sub-carrier from MFIN pin Modulation signal from the internal analog part, default NRZ coding without sub-carrier from MFIN pin. Only valid for transfer speeds above 106 kbit/s. 5 to 0 RxWait After data transmission, the activation of the receiver is delayed for RxWait bit-clocks. During this `frame guard time' any signal at pin Rx is ignored.This parameter is ignored by the receive command. All other commands (e.g. Transceive, MFAuthent) use this parameter. The counter starts immediately after the external RF field is switched on. 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 29 of 109 NXP Semiconductors MFRC522 Contactless Reader IC 9.2.2.9 RxThresholdReg Selects thresholds for the bit decoder. Table 55: Bit Symbol Access Rights Table 56: Bit 7 to 4 3 2 to 0 RxThresholdReg register (address 18h); reset value: 84h 7 6 MinLevel r/w 5 4 3 RFU 2 1 CollLevel r/w 0 Description of RxThresholdReg bits Symbol MinLevel CollLevel Description Defines the minimum signal strength at the decoder input that shall be accepted. If the signal strength is below this level, it is not evaluated. Reserved for future use. Defines the minimum signal strength at the decoder input that has to be reached by the weaker half-bit of the Manchester-coded signal to generate a bit-collision relatively to the amplitude of the stronger half-bit. 9.2.2.10 DemodReg Defines demodulator settings. Table 57: Bit Symbol Access Rights Table 58: Bit 7 to 6 DemodReg register (address 19h); reset value: 4Dh 7 AddIQ r/w 6 5 FixIQ r/w 4 RFU 3 TauRcv r/w 2 1 TauSync r/w 0 Description of DemodReg bits Symbol AddIQ Description Defines the use of I and Q channel during reception Remark: FixIQ has to be set to logic 0 to enable the following settings. Value 00 01 10 11 Description Select the stronger channel Select the stronger channel and freeze the selected during communication Reserved Reserved 5 FixIQ If set to logic 1 and the bits AddIQ are set to X0b, the reception is fixed to I channel. If set to logic 1 and the bits AddIQ are set to X1b, the reception is fixed to Q channel. 4 3 to 2 1 to 0 TauRcv TauSync Reserved for future use. Changes the time constant of the internal PLL during data reception. Remark: If set to 00b, the PLL is frozen during data reception. Changes the time constant of the internal PLL during burst. 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 30 of 109 NXP Semiconductors MFRC522 Contactless Reader IC 9.2.2.11 Reserved Functionality is reserved for further use. Table 59: Bit Symbol Access Rights Table 60: Bit 7 to 0 Description of Reserved register bits Symbol Description Reserved for future use. Reserved register (address 1Ah); reset value: 00h 7 6 5 4 RFU 3 2 1 0 9.2.2.12 Reserved Functionality is reserved for further use. Table 61: Bit Symbol Access Rights Table 62: Bit 7 to 0 Description of Reserved register bits Symbol Description Reserved for future use. Reserved register (address 1Bh); reset value: 00h 7 6 5 4 RFU 3 2 1 0 9.2.2.13 MfTxReg Controls some MIFARE(R) communication transmit parameters Table 63: Bit Symbol Access Rights Table 64: Bit 7 to 2 1 to 0 MfTxReg register (address 1Ch); reset value: 62h 7 6 5 RFU 4 3 2 1 TxWait r/w 0 Description of MifNFCReg bits Symbol TxWait Description Reserved for future use. These bits define the additional response time. Per default 7 bits are added to the value of the register bit. 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 31 of 109 NXP Semiconductors MFRC522 Contactless Reader IC 9.2.2.14 MfRxReg Table 65: Bit Symbol Access Rights Table 66: Bit 7 to 5 4 MfRxReg register (address 1Dh); reset value: 00h 7 6 RFU 5 4 Parity Disable r/w 3 2 RFU 1 0 Description of ManualRCVReg bits Symbol Parity Disable Description Reserved for future use. If this bit is set to logic 1, the generation of the Parity bit for transmission and the Parity-Check for receiving is switched off. The received Parity bit is handled like a data bit. Reserved for future use. 3 to 0 - 9.2.2.15 Reserved Functionality is reserved for further use. Table 67: Bit Symbol Access Rights Table 68: Bit 7 to 0 Description of Reserved register bits Symbol Description Reserved for future use. Reserved register (address 1Eh); reset value: 00h 7 6 5 4 RFU 3 2 1 0 9.2.2.16 SerialSpeedReg Selects the speed of the serial UART interface. Table 69: Bit Symbol Access Rights Table 70: Bit 7 to 5 4 to 0 SerialSpeedReg register (address 1Fh); reset value: EBh 7 6 BR_T0 r/w 5 4 3 2 BR_T1 r/w 1 0 Description of SerialSpeedReg bits Symbol BR_T0 BR_T1 Description Factor BR_T0 to adjust the transfer speed, for description see Section 10.3.2 "Selection of the transfer speeds". Factor BR_T1 to adjust the transfer speed, for description see Section 10.3.2 "Selection of the transfer speeds". 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 32 of 109 NXP Semiconductors MFRC522 Contactless Reader IC 9.2.3 Page 2: Configuration 9.2.3.1 Reserved Functionality is reserved for further use. Table 71: Bit Symbol Access Rights Table 72: Bit 7 to 0 Description of Reserved register bits Symbol Description Reserved for future use. Reserved register (address 20h); reset value: 00h 7 6 5 4 RFU 3 2 1 0 9.2.3.2 CRCResultReg Shows the actual MSB and LSB values of the CRC calculation. Remark: The CRC is split into two 8-bit register. Table 73: Bit Symbol Access Rights Table 74: Bit 7 to 0 CRCResultReg register (address 21h); reset value: FFh 7 6 5 4 r 3 2 1 0 CRCResultMSB Description of CRCResultReg higher bits Symbol CRCResultMSB Description This register shows the actual value of the most significant byte of the CRCResultReg register. It is valid only if bit CRCReady in register Status1Reg is set to logic 1. Table 75: Bit Symbol Access Rights Table 76: Bit 7 to 0 CRCResultReg register (address 22h); reset value: FFh 7 6 5 4 r 3 2 1 0 CRCResultLSB Description of CRCResultReg lower bits Symbol CRCResultLSB Description This register shows the actual value of the least significant byte of the CRCResult register. It is valid only if bit CRCReady in register Status1Reg is set to logic 1. 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 33 of 109 NXP Semiconductors MFRC522 Contactless Reader IC 9.2.3.3 Reserved Functionality is reserved for further use. Table 77: Bit Symbol Access Rights Table 78: Bit 7 to 0 Description of Reserved register bits Symbol Description Reserved for future use. Reserved register (address 23h); reset value: 88h 7 6 5 4 RFU 3 2 1 0 9.2.3.4 ModWidthReg Controls the setting of modulation width. Table 79: Bit Symbol Access Rights Table 80: Bit 7 to 0 Description of ModWidthReg bits Symbol ModWidth Description These bits define the width of the Miller modulation as multiples of the carrier frequency (ModWidth +1/fc). The maximum value is half the bit period. ModWidthReg register (address 24h); reset value: 26h 7 6 5 4 r/w 3 2 1 0 ModWidth 9.2.3.5 Reserved Functionality is reserved for further use. Table 81: Bit Symbol Access Rights Table 82: Bit 7 to 0 Description of Reserved register bits Symbol Description Reserved for future use. Reserved register (address 25h); reset value: 87h 7 6 5 4 RFU 3 2 1 0 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 34 of 109 NXP Semiconductors MFRC522 Contactless Reader IC 9.2.3.6 RFCfgReg Configures the receiver gain. Table 83: Bit Symbol Access Rights Table 84: Bit 7 6 to 4 RFCfgReg register (address 26h); reset value: 48h 7 RFU 6 5 RxGain r/w 4 3 2 RFU 1 0 Description of RFCfgReg bits Symbol RxGain Description Reserved for future use. This register defines the receivers signal voltage gain factor: Value 000 001 010 011 100 101 110 111 Description 18 dB 23 dB 18 dB 23 dB 33 dB 38 dB 43 dB 48 dB 3 to 0 - .Reserved for future use. 9.2.3.7 GsNReg Selects the conductance for the N-driver of the antenna driver pins TX1 and TX2 when the driver is switched on. Table 85: Bit Symbol Access Rights Table 86: Bit 7 to 4 GsNReg register (address 27h); reset value: 88h 7 6 CWGsN r/w 5 4 3 2 ModGsN r/w 1 0 Description of GsNOnReg bits Symbol CWGsN Description The value of this register defines the conductance of the output N-driver during times of no modulation. This may be used to regulate the output power and subsequently current consumption and operating distance. Remark: The conductance value is binary weighted. During soft Power-down mode the highest bit is forced to 1. This value is only used if the driver TX1 or TX2 are switched on. 3 to 0 ModGsN The value of this register defines the conductance of the output N-driver for the time of modulation. This may be used to regulate the modulation index. Remark: The conductance value is binary weighted. During soft Power-down mode the highest bit is forced to 1. This value is only used if the driver TX1 or Tx2 are switched on. 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 35 of 109 NXP Semiconductors MFRC522 Contactless Reader IC 9.2.3.8 CWGsPReg Defines the conductance of the P-driver during times of no modulation Table 87: Bit Symbol Access Rights Table 88: Bit 7 to 6 5 to 0 CWGsPReg register (address 28h); reset value: 20h 7 RFU 6 5 4 3 CWGsP r/w 2 1 0 Description of CWGsPReg bits Symbol CWGsP Description Reserved for future use. The value of this register defines the conductance of the output P-driver. This may be used to regulate the output power and subsequently current consumption and operating distance. Remark: The conductance value is binary weighted. During soft Power-down mode the highest bit is forced to 1. 9.2.3.9 ModGsPReg Defines the driver P-output conductance during modulation. Table 89: Bit Symbol Access Rights Table 90: Bit 7 to 6 5 to 0 ModGsPReg register (address 29h); reset value: 20h 7 RFU 6 5 4 3 ModGsP r/w 2 1 0 Description of ModGsPReg bits Symbol ModGsP Description Reserved for future use. The value of this register defines the conductance of the output P-driver for the time of modulation. This may be used to regulate the modulation index. Remark: The conductance value is binary weighted. During soft Power-down mode the highest bit is forced to 1. If Force100ASK is set to logic 1, the value of ModGsP has no effect. 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 36 of 109 NXP Semiconductors MFRC522 Contactless Reader IC 9.2.3.10 TMode Register, TPrescaler Register Defines settings for the timer. Remark: The Prescaler value is split over two registers. Table 91: Bit Symbol Access Rights Table 92: Bit 7 TModeReg register (address 2Ah); reset value: 00h 7 TAuto r/w 6 TGated r/w 5 4 TAutoRestart r/w 3 2 r/w 1 0 TPrescaler_Hi Description of TModeReg bits Symbol TAuto Description Set to logic 1, the timer starts automatically at the end of the transmission in all communication modes at all speeds. The timer stops immediately after receiving the first data bit if the bit RxMultiple in the register RxModeReg is not set. If RxMultiple is set to logic 1, the timer never stops. In this case the timer can be stopped by setting the bit TStopNow in register ControlReg to logic 1. Set to logic 0 indicates, that the timer is not influenced by the protocol. 6 to 5 TGated The internal timer is running in gated mode. Remark: In the gated mode, the bit TRunning is logic 1 when the timer is enabled by the register bits. This bit does not influence the gating signal. Value 00 01 10 11 Description Non gated mode Gated by MFIN Gated by AUX1 Gated by A3 4 TAutoRestart Set to logic 1, the timer automatically restart its count-down from TReloadValue, instead of counting down to zero. Set to logic 0 the timer decrements to 0 and the bit TimerIRq is set to logic 1. 3 to 0 TPrescaler_Hi Defines higher 4 bits for TPrescaler. The following formula is used to calculate fTimer: fTimer = 6.78 MHz/TPreScaler. For detailed description see Section 13 "Timer Unit". Table 93: Bit Symbol Access Rights Table 94: Bit 7 to 0 TPrescalerReg register (address 2Bh); reset value: 00h 7 6 5 4 3 2 TPrescaler_Hi r/w 1 0 Description of TPrescalerReg bits Symbol Description The following formula is used to calculate fTimer: fTimer = 6.78 MHz/TPreScaler. For detailed description see Section 13 "Timer Unit". TPrescaler_Lo Defines lower 8 bits for TPrescaler. 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 37 of 109 NXP Semiconductors MFRC522 Contactless Reader IC 9.2.3.11 TReloadReg Describes the 16 bit long timer reload value. Remark: The Reload value is split into two 8-bit registers. Table 95: Bit Symbol Access Rights Table 96: Bit 7 to 0 00 TReloadReg (Higher bits) register (address 2Ch); reset value: 00h 7 6 5 4 r/w 3 2 1 0 TReloadVal_Hi Description of higher TReloadReg bits Symbol Description With a start event the timer loads the TReloadVal. Changing this register affects the timer only at the next start event. TReloadVal_Hi Defines the higher 8 bits for the TReloadReg. Table 97: Bit Symbol Access Rights Table 98: Bit 7 to 0 00 TReloadReg (Lower bits)register (address 2Dh); reset value: 00h 7 6 5 4 r/w 3 2 1 0 TReloadVal_Lo Description of lower TReloadReg bits Symbol Description With a start event the timer loads the TReloadVal. Changing this register affects the timer only at the next start event. TReloadVal_Lo Defines the lower 8 bits for the TReloadReg. 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 38 of 109 NXP Semiconductors MFRC522 Contactless Reader IC 9.2.3.12 TCounterValReg Contains the current value of the timer. Remark: The Counter value is split into two 8-bit register. Table 99: Bit Symbol Access Rights TCounterValReg (Higher bits) register (address 2Eh); reset value: XXh 7 6 5 4 r 3 2 1 0 TCounterVal_Hi Table 100: Description of higher TCounterValReg bits Bit 7 to 0 Symbol TCounterVal_Hi Description Current value of the timer, higher 8 bits. Table 101: TCounterValReg (Lower bits) register (address 2Fh); reset value: XXh Bit Symbol Access Rights 7 6 5 4 r 3 2 1 0 TCounterVal_Lo Table 102: Description of lower TCounterValReg bits Bit 7 to 0 Symbol Description TCounterVal_Lo Current value of the timer, lower 8 bits. 9.2.4 Page 3: Test 9.2.4.1 Reserved Functionality is reserved for further use. Table 103: Reserved register (address 30h); reset value: 00h Bit Symbol Access Rights Table 104: Description of Reserved register bits Bit 7 to 0 Symbol Description Reserved for future use. 7 6 5 4 RFU 3 2 1 0 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 39 of 109 NXP Semiconductors MFRC522 Contactless Reader IC 9.2.4.2 TestSel1Reg General test signal configuration. Table 105: TestSel1Reg register (address 31h); reset value: 00h Bit Symbol Access Rights 7 6 5 RFU 4 3 2 1 TstBusBitSel r/w 0 Table 106: Description of TestSel1Reg bits Bit 7 to 3 2 to 0 Symbol TstBusBitSel Description Reserved for future use. Select the TestBus bit from the testbus to be propagated to MFOUT. 9.2.4.3 TestSel2Reg General test signal configuration and PRBS control Table 107: TestSel2Reg register (address 32h); reset value: 00h Bit Symbol Access Rights 7 TstBusFlip r/w 6 PRBS9 r/w 5 PRBS15 r/w 4 3 2 TestBusSel r/w 1 0 Table 108: Description of TestSel2Reg bits Bit 7 Symbol TstBusFlip Description If set to logic 1, the testbus is mapped to the parallel port by the following order: TstBusBit4,TstBusBit3, TstBusBit2,TstBusBit6,TstsBusBit5, TstBusBit0. See Section 19 "Testsignals". 6 PRBS9 Starts and enables the PRBS9 sequence according ITU-TO150. Remark: All relevant registers to transmit data have to be configured before entering PRBS9 mode. The data transmission of the defined sequence is started by the send command. 5 PRBS15 Starts and enables the PRBS15 sequence according ITU-TO150. Remark: All relevant registers to transmit data have to be configured before entering PRBS15 mode. The data transmission of the defined sequence is started by the send command. 4 to 0 TestBusSel Selects the testbus. See Section 19 "Testsignals" 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 40 of 109 NXP Semiconductors MFRC522 Contactless Reader IC 9.2.4.4 TestPinEnReg Enables the pin output driver on the test bus. Table 109: TestPinEnReg register (address 33h); reset value: 80h Bit Symbol Access Rights 7 RS232LineEn r/w 6 5 4 r/w 3 2 1 0 RFU TestPinEn Table 110: Description of TestPinEnReg bits Bit 7 6 to 1 Symbol RS232LineEn TestPinEn Description Set to logic 0, the lines MX and DTRQ for the serial UART are disabled. Enables the pin output driver on D1 to D7. Example: Setting bit 1 to logic 1 enables D1 Setting bit 5 to logic 1 enables D5 Remark: If the SPI interface is used only D1 to D4 can be used. If the serial UART interface is used and RS232LineEn is set to logic 1 only D1 to D4 can be used. 0 Reserved for future use. 9.2.4.5 TestPinValueReg Defines the values for the test port when it is used as I/O. Table 111: TestPinValueReg register (address 34h); reset value: 00h Bit Symbol Access Rights 7 UseIO r/w 6 5 4 r/w 3 2 1 0 RFU TestPinValue Table 112: Description of TestPinValueReg bits Bit 7 Symbol UseIO Description Set to logic 1, this bit enables the I/O functionality for the test port if one of the serial interfaces is used. The input / ouput behaviour is defined by TestPinEn in register TestPinEnReg. The value for the output behaviour is defined in the bits TestPinVal. Defines the value of the test port, when it is used as I/O. Each output has to be enabled by the TestPinEn bits in register TestPinEnReg. Remark: Reading the register indicates the actual status of the pins D6 - D1 if UseIO is set to logic 1. If UseIO is set to logic 0, the value of the register TestPinValueReg is read back. 0 Reserved for future use. 6 to 0 TestPinValue 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 41 of 109 NXP Semiconductors MFRC522 Contactless Reader IC 9.2.4.6 TestBusReg Shows the status of the internal testbus. Table 113: TestBusReg register (address 35h); reset value: XXh Bit Symbol Access Rights Table 114: Description of TestBusReg bits Bit 7 to 0 Symbol TestBus Description Shows the status of the internal test bus. The test bus is selected by the register TestSel2Reg. See Section 19 "Testsignals". 7 6 5 4 TestBus r 3 2 1 0 9.2.4.7 AutoTestReg Controls the digital selftest. Table 115: AutoTestReg register (address 36h); reset value: 40h Bit Symbol Access Rights 7 RFU 6 AmpRcv r/w 5 RFT 4 3 2 SelfTest r/w 1 0 Table 116: Description of AutoTestReg bits Bit 7 6 Symbol AmpRcv Description Reserved for production tests. If set to logic 1, the internal signal processing in the receiver chain is performed non-linear. This increases the operating distance in communication modes at 106 kbit/s. Remark: Due to the non linearity the effect of the bits MinLevel and CollLevel in the register RxThreshholdReg are as well non linear. 5 to 4 3 to 0 SelfTest Reserved for production tests. Enables the digital self test. The selftest can be started by the selftest command in the command register. The selftest is enabled by 1001b. Remark: For default operation the selftest has to be disabled by 0000b. 9.2.4.8 VersionReg Shows the version. Table 117: VersionReg register (address 37h); reset value: XXh Bit Symbol Access Rights Table 118: Description of VersionReg bits Bit 7 to 0 Symbol Version Description Indicates current version. Remark: The current version for MFRC522 is 90h or 91h. 7 6 5 4 Version r 3 2 1 0 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 42 of 109 NXP Semiconductors MFRC522 Contactless Reader IC 9.2.4.9 AnalogTestReg Controls the pins AUX1 and AUX2 Table 119: AnalogTestReg register (address 38h); reset value: 00h Bit Symbol Access Rights 7 6 r/w 5 4 3 2 r/w 1 0 AnalogSelAux1 AnalogSelAux2 Table 120: Description of AnalogTestReg bits Bit 7 to 4 3 to 0 Symbol Description AnalogSelAux1 Controls the AUX pin. AnalogSelAux2 Remark: All test signals are described in Section 19 "Testsignals". Value 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 Description Tristate Output of TestDAC1 (AUX1), output of TestDAC2 (AUX2) [1] Testsignal Corr1 [1] Reserved Testsignal MinLevel [1] Testsignal ADC channel I [1] Testsignal ADC channel Q [1] Reserved Reserved, Testsignal for production test [1] Reserved HIGH LOW TxActive At 106 kbit/s: HIGH during Startbit, Databit, Parity and CRC. At 212, 424 and 848 kbit/s: High during Data and CRC. 1101 RxActive At 106 kbit/s: High during Databit, Parity and CRC. At 212, 424 and 848 kbit/s: High during Data and CRC. 1110 Subcarrier detected 106 kbit/s: not applicable 212, 424 and 848 kbit/s: High during last part of Data and CRC. 1111 [1] Test bus bit as defined by the TstBusBitSel in register TestSel1Reg. Remark: Current output. The use of 1 k pull-down resistor on AUX is recommended 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 43 of 109 NXP Semiconductors MFRC522 Contactless Reader IC 9.2.4.10 TestDAC1Reg Defines the test values for TestDAC1. Table 121: TestDAC1Reg register (address 39h); reset value: XXh Bit Symbol Access Rights 7 RFU 6 5 4 3 r/w 2 1 0 TestDAC1 Table 122: Description of TestDAC1Reg bits Bit 7 6 5 to 0 Symbol TestDAC1 Description Reserved for production tests. Reserved for future use. Defines the test value for TestDAC1. The output of the DAC1 can be switched to AUX1 by setting AnalogSelAux1 to 0001b in register AnalogTestReg. 9.2.4.11 TestDAC2Reg Defines the test value for TestDAC2. Table 123: TestDAC2Reg register (address 3Ah); reset value: XXh Bit Symbol Access Rights 7 RFU 6 5 4 3 r/w 2 1 0 TestDAC2 Table 124: Description ofTestDAC2Reg bits Bit 7 to 6 5 to 0 Symbol TestDAC2 Description Reserved for future use. Defines the testvalue for TestDAC2. The output of the DAC2 can be switched to AUX2 by setting AnalogSelAux2 to 0001b in register AnalogTestReg. 9.2.4.12 TestADCReg Shows the actual value of ADC I and Q channel. Table 125: TestADCReg register (address 3Bh); reset value: XXh Bit Symbol Access Rights 7 6 ADC_I r 5 4 3 2 ADC_Q r 1 0 Table 126: Description of TestADCReg bits Bit 7 to 4 3 to 0 Symbol ADC_I ADC_Q Description Shows the actual value of ADC I channel. Shows the actual value of ADC Q channel. 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 44 of 109 NXP Semiconductors MFRC522 Contactless Reader IC 9.2.4.13 Reserved Functionality reserved for production test. Table 127: Reserved register (address 3Ch); reset value: FFh Bit Symbol Access Rights Table 128: Description of Reserved register bits Bit 7 to 0 Symbol Description Reserved for production tests. 7 6 5 4 RFT 3 2 1 0 Table 129: Reserved register (address 3Dh); reset value: 00h Bit Symbol Access Rights Table 130: Description of Reserved register bits Bit 7 to 0 Symbol Description Reserved for production tests. 7 6 5 4 RFT 3 2 1 0 Table 131: Reserved register (address 3Eh); reset value: 03h Bit Symbol Access Rights Table 132: Description of Reserved register bits Bit 7 to 0 Symbol Description Reserved for production tests. 7 6 5 4 RFT 3 2 1 0 Table 133: Reserved register (address 3Fh); reset value: 00h Bit Symbol Access Rights Table 134: Description of Reserved register bits Bit 7 to 0 Symbol Description Reserved for production tests. 7 6 5 4 RFT 3 2 1 0 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 45 of 109 NXP Semiconductors MFRC522 Contactless Reader IC 10. DIGITAL Interfaces 10.1 Automatic -Controller Interface Type Detection The MFRC522 supports direct interfacing of various hosts as the SPI, I2C and serial UART interface type. The MFRC522 resets its interface and checks the current host interface type automatically having performed a Power-On or Hard Reset. The MFRC522 identifies the host interface by the means of the logic levels on the control pins after the Reset Phase. This is done by a combination of fixed pin connections.The following table shows the different configurations: Table 135: Connection Scheme for detecting the different Interface Types MFRC522 Pin SDA IC EA D7 D6 D5 D4 D3 D2 D1 Pin behavior UART Serial Interface Types SPI I2C SDA 1 EA SCL ADR_0 ADR_1 ADR_2 ADR_3 ADR_4 ADR_5 In/Out RX 0 0 TX MX DTRQ Input NSS 0 1 MISO MOSI SCK Output Remark: Overview on the pin behavior 10.2 SPI Compatible interface A serial peripheral interface (SPI compatible) is supported to enable high speed communication to the host. The SPI Interface can handle data speed of up to 10 Mbit/s. In the communication with a host MFRC522 acts as a slave receiving data from the external host for register settings and to send and receive data relevant for the communication on the RF interface. 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 46 of 109 NXP Semiconductors MFRC522 Contactless Reader IC 10.2.1 General An interface compatible to an SPI interface enables a high-speed serial communication between the MFRC522 and a -Controller for the communication. The implemented SPI compatible interface is according to a standard SPI interface. For timing specification refer to Section 23.8 "Timing for the SPI compatible interface". RC522 SCK SCK MOSI MOSI MISO MISO NSS NSS Fig 7. Connection to host with SPI The MFRC522 acts as a slave during the SPI communication. The SPI clock SCK has to be generated by the master. Data communication from the master to the slave uses the Line MOSI. Line MISO is used to send data back from the MFRC522 to the master. On both lines (MOSI, MISO) each data byte is sent by MSB first. Data on MOSI line should be stable on rising edge of the clock line and can changed on falling edge. The same is valid for the MISO line. Data is provided by the MFRC522 on falling edge and is stable during rising edge. 10.2.2 Read data To read out data using the SPI compatible interface the following byte order has to be used. It is possible to read out up to n-data bytes. The first sent byte defines both, the mode itself and the address byte. Table 136: Byte Order for MOSI and MISO byte 0 MOSI MISO adr 0 X byte 1 adr 1 data 0 byte 2 adr 2 data 1 to ........ ........ byte n adr n data n-1 byte n+1 00 data n Remark: The most significant bit (MSB) has to be send first. 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 47 of 109 NXP Semiconductors MFRC522 Contactless Reader IC 10.2.3 Write data To write data to the MFRC522 using the SPI interface the following byte order has to be used. It is possible to write out up to n-data bytes by only sending one's address byte. The first send byte defines both, the mode itself and the address byte. Table 137: Byte Order for MOSI and MISO byte 0 MOSI MISO adr 0 X byte 1 data 0 X byte 2 data 1 X to ........ ........ byte n data n-1 X byte n+1 data n X Remark: The most significant bit (MSB) has to be send first. 10.2.4 Address byte The address byte has to fulfil the following format: The MSB bit of the first byte defines the used mode. To read data from the MFRC522 the MSB bit is set to logic 1. To write data to the MFRC522 the MSB bit has to be set to logic 0. The bits 6 to 1 define the address and the LSB shall be set to logic 0. Table 138. Address byte 0 register; address MOSI 7 1 (read) 0 (write) MSB 6 5 4 address 3 2 1 0 RFU LSB 10.3 UART Interface 10.3.1 Connection to a host RX RX TX TX DTRQ RC522 DTRQ MX MX Fig 8. Connection to -Controllers with UART. Remark: DTRQ and MX can be disabled by clearing the bit RS232LineEn in register TestPinEnReg. 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 48 of 109 NXP Semiconductors MFRC522 Contactless Reader IC 10.3.2 Selection of the transfer speeds The internal UART interface is compatible to an RS232 serial interface. Table 140 "Selectable transfer speeds" describes examples for different transfer speeds and relevant register settings. The resulting transfer speed error is less than 1.5% for all described transfer speeds. The default transfer speed is 9.6 kbit/s. To change the transfer speed, the host controller has to write a value for the new transfer speed to the register SerialSpeedReg. The bits BR_T0 and BR_T1 define factors to set the transfer speed in the SerialSpeedReg. Table 139 "Settings of BR_T0 and BR_T1" describes the settings of BR_T0 and BR_T1. Table 139: Settings of BR_T0 and BR_T1 BR_T0 factor BR_T0 range BR_T1 0 1 1 to 32 1 1 2 2 3 4 4 8 5 16 6 32 7 64 33 to 64 33 to 64 33 to 64 33 to 64 33 to 64 33 to 64 33 to 64 Table 140: Selectable transfer speeds Transfer Speed [bit/s] 7.2 k 9.6 k 14.4 k 19.2 k 38.4 k 57.6 k 115.2 k 128 k 230.4 k 460.8 k 921.6 k 1228.8 k SerialSpeedReg decimal 250 235 218 203 171 154 122 116 90 58 28 21 heximal FAh EBh DAh CBh ABh 9Ah 7Ah 74h 5Ah 3Ah 1Ch 15h -0.25% 0.32% -0.25% 0.32% 0.32% -0.25% -0.25% -0.06% -0.25% -0.25% 1.45% 0.32% Transfer Speed Accuracy The selectable transfer speeds as shown in Table 140 "Selectable transfer speeds" are calculated according to the following formulas: if BR_T0=0: transfer speed = 27.12 MHz/(BR_T1+1) if BR_T0>0: transfer speed = 27.12 MHz/(BR_T1 +33)/2^(BR_T0 -1) Remark: Transfer speeds above 1228.8 k are not supported. 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 49 of 109 NXP Semiconductors MFRC522 Contactless Reader IC 10.3.3 Framing Table 141: UART Framing Length Start bit Data bits Stop bit 1 bit 8 bits 1 bit Value 0 Data 1 Remark: For data and address bytes the LSB bit has to be sent first. No parity bit is used during transmission. Read data: To read out data using the UART interface the flow described below has to be used. The first send byte defines both the mode itself and the address. Table 142: Byte Order to Read Data byte 0 RX TX adr data 0 byte 1 Fig 9. Schematic Diagram to Read Data 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 50 of 109 NXP Semiconductors MFRC522 Contactless Reader IC Write data: To write data to the MFRC522 using the UART interface the following structure has to be used. The first send byte defines both, the mode itself and the address. Table 143: Byte Order to Write Data byte 0 RX TX adr 0 byte 1 data 0 adr 0 Fig 10. Schematic Diagram to Write Data. Remark: The data byte can be send directly after the address byte on RX. Address byte: The address byte has to fulfil the following format: The MSB of the first byte sets the used mode. To read data from the MFRC522 the MSB is set to logic 1. To write data to the MFRC522 the MSB has to be set to logic 0. The bit 6 is reserved for further use and the bits 5 to 0 define the address. Table 144. Address byte 0 register; address MOSI 7 1 (read) 0 (write) MSB 6 RFU 5 4 3 address LSB 2 1 0 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 51 of 109 NXP Semiconductors MFRC522 Contactless Reader IC 10.4 I2C Bus Interface An Inter IC (I2C) bus interface is supported to enable a low cost, low pin count serial bus interface to the host. The implemented I2C interface is implemented according the NXP Semiconductors I2C interface specification, rev. 2.1, January 2000. The implemented interface can only act in Slave mode. Therefore no clock generation and access arbitration is implemented in the MFRC522. pullup network pullup network RC522 C configuration wiring SDA SCL I2C EA D[1..6] Fig 11. I2C interface. 10.4.1 General The implemented interface is conform to the I2C-bus specification version 2.1, January 2000. The MFRC522 can act as a slave receiver or slave transmitter in Standard mode, Fast mode and High-speed mode. SDA is a bi-directional line, connected to a positive supply voltage via a current-source or a pull-up resistor. Both lines SDA and SCL are set to HIGH level if no data is transmitted. The MFRC522 has a tri-state output stage to perform the wired-AND function. Data on the I2C-bus can be transferred at data rates of up to 100 kbit/s in Standard mode, up to 400 kbit/s in the Fast mode or up to 3.4 Mbit/s in the High-speed mode. If the I2C interface is selected, a spike suppression according to the I2C interface specification on SCL and SDA is activated. For timing requirements refer to Section 23.9 "I2C Timing" 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 52 of 109 NXP Semiconductors MFRC522 Contactless Reader IC 10.4.2 Data validity Data on the SDA line shall be stable during the HIGH period of the clock. The HIGH or LOW state of the data line shall only change when the clock signal on SCL is LOW. Fig 12. Bit transfer on the I2C-bus. 10.4.3 START and STOP conditions To handle the data transfer on the I2C-bus, unique START (S) and STOP (P) conditions are defined. A START condition is defined with a HIGH to LOW transition on the SDA line while SCL is HIGH. A STOP condition is defined with a LOW to HIGH transition on the SDA line while SCL is HIGH. The master always generates the START and STOP conditions. The bus is considered to be busy after the START condition. The bus is considered to be free again a certain time after the STOP condition. The bus stays busy if a repeated START (Sr) is generated instead of a STOP condition. In this respect, the START (S) and repeated START (Sr) conditions are functionally identical. Therefore, the S symbol will be used as a generic term to represent both the START and repeated START (Sr) conditions. Fig 13. START and STOP conditions. 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 53 of 109 NXP Semiconductors MFRC522 Contactless Reader IC 10.4.4 Byte format Each byte has to be followed by an acknowledge bit. Data is transferred with the MSB first, see Figure 16 "First byte following the START procedure.". The number of transmitted bytes during one data transfer is unrestricted but shall fulfil the read/ write cycle format. 10.4.5 Acknowledge An acknowledge at the end of one data byte is mandatory. The acknowledge-related clock pulse is generated by the master. The transmitter of data, either master or slave, releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver shall pull down the SDA line during the acknowledge clock pulse so that it remains stable LOW during the HIGH period of this clock pulse. The master can then generate either a STOP (P) condition to stop the transfer, or a repeated START (Sr) condition to start a new transfer. A master-receiver shall indicate the end of data to the slave- transmitter by not generating an acknowledge on the last byte that was clocked out by the slave. The slave-transmitter shall release the data line to allow the master to generate a STOP (P) or repeated START (Sr) condition. Fig 14. Acknowledge on the I2C- bus. 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 54 of 109 NXP Semiconductors MFRC522 Contactless Reader IC Fig 15. Data transfer on the I2C- bus. 10.4.6 7-BIT ADDRESSING During the I2C-bus addressing procedure, the first byte after the START condition is used to determine which slave will be selected by the master. As an exception several address numbers are reserved. During device configuration, the designer has to ensure, that no collision with these reserved addresses is possible. Check the corresponding I2C specification for a complete list of reserved addresses. The I2C address specification is dependent on the definition of the EA Pin. Immediately after releasing the reset pin or after power on reset, the device defines the I2C address according EA pin. If EA Pin is set to LOW than for all MFRC522 devices the upper 4 bits of the device bus address are reserved by NXP and set to 0101(bin). The remaining 3 bits (ADR_0, ADR_1, ADR_2) of the Slave Address can freely configured by the customer in order to prevent collisions with other I2C devices. If EA Pin is set to HIGH than ADR_0 to ADR_5 can be completely specified at the external pins according to Table Table 135 "Connection Scheme for detecting the different Interface Types". ADR_6 is always set to logic 0. In both modes, the external address coding is latched immediately after releasing the reset condition. Further changes at the used pins are not taken into consideration. Depending on the external wiring, the I2C address pins could be used for test signal output. 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 55 of 109 NXP Semiconductors MFRC522 Contactless Reader IC Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Fig 16. First byte following the START procedure. 10.4.7 Register Write Access To write data from the host controller via I2C to a specific register of the MFRC522 the following frame format shall be used. The first byte of a frame indicates the device address according to the I2C rules. The second byte indicates the register address followed by up to n-data bytes. In one frame all n-data bytes are written to the same register address. This enables for example a fast FIFO access. The read/write bit shall be set to logic 0. 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 56 of 109 NXP Semiconductors MFRC522 Contactless Reader IC 10.4.8 Register Read Access To read out data from a specific register address of the MFRC522 the host controller shall use the procedure: First a write access to the specific register address has to be performed as indicated in the following frame. The first byte of a frame indicates the device address according to the I2C rules. The second byte indicates the register address. No data bytes are added. The read/write bit shall be 0. Having performed this write access, the read access can start. The host has to send the device address of the MFRC522. As an answer to this the MFRC522 responds with the content of this register. In one frame all n-data bytes could be read from the same register address. This enables for example a fast FIFO access or register polling. The read/write bit shall be set to logic 1. Write Cycle SA I2C slave address A7-A0 0 (W) Ack 0 0 Joiner register address A5-A0 Ack [0..n] DATA [7..0] Ack SO Read Cycle I2C slave address A7-A0 0 (W) Joiner register address A5-A0 SA Ack 0 0 Ack SO Optional, if the previous access was on the same register address 0..n I2C slave address A7-A0 1 (R) DATA [7..0] SA Ack [0..n] Ack sent by master DATA [7..0] Nack SO sent by slave SA SO ACK Nack (W) (R) start condition stop condition acknowledge not acknowlege write cycle read cycle Fig 17. Register Read and Write Access 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 57 of 109 NXP Semiconductors MFRC522 Contactless Reader IC 10.4.9 HS mode In High-speed mode (HS mode) the device can transfer information at data rates of up to 3.4 Mbit/s, it remains fully downward compatible with Fast- or Standard mode (F/S mode) for bi-directional communication in a mixed-speed bus system. 10.4.10 High Speed Transfer To achieve a data rates of up to 3.4 Mbit/s the following improvements have been made to the regular I2C-bus behavior. * The inputs of the device in HS mode incorporates spike suppression and a Schmitt-trigger at the SDA and SCL inputs with different timing constants compared to F/S mode. * The output buffers of the device in HS mode incorporates slope control of the falling edges of the SDA and SCL signals with different fall time compared to F/S mode. 10.4.11 Serial Data transfer Format in HS mode Serial data transfer format in HS mode meets the Standard mode I2C-bus specification. HS mode can only commence after the following conditions (all of which are in F/S mode): 1. START condition (S) 2. 8-bit master code (00001XXX) 3. Not-acknowledge bit (A) The active master then sends a repeated START condition (Sr) followed by a 7-bit slave address with a R/W bit address, and receives an acknowledge bit (A) from the selected MFRC522. Data transfer continues in in Hs-mode after the next repeated START (Sr), and only switches back to F/S-mode after a STOP condition (P). To reduce the overhead of the master code, it's possible that a master links a number of Hs-mode transfers, separated by repeated START conditions (Sr). Fig 18. I2C HS mode protocol switch 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 58 of 109 NXP Semiconductors MFRC522 Contactless Reader IC Fig 19. I2C HS mode protocol frame 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 59 of 109 NXP Semiconductors MFRC522 Contactless Reader IC 10.4.12 Switching from F/S to HS mode and Vice Versa After reset and initialization, the MFRC522 is in Fast mode (which is in effect F/S mode as Fast mode is downward compatible to Standard mode). The connected MFRC522 recognizes the "S 00001XXX A" sequence and switches its internal circuitry from the Fast mode setting to the HS mode setting. Following actions are taken: 1. Adapt the SDA and SCL input filters according to the spike suppression requirement in HS mode. 2. Adapt the slope control of the SDA output stages. For system configurations, where no other I2C devices are involved in the communication, have an additional possibility to switch to HS-mode. By setting the bit I2CForceHS in register Status2Reg to logic 1, the HS mode is entered. Setting this bit to logic 1 changes the HS-mode permanent meaning that sending the master code is no longer necessary. This is not according the specification and should only be used when no other devices are connected on the bus. Spikes on the I2C lines shall be avoided because of the reduced spike suppression. 10.4.13 MFRC522 at Lower Speed modes MFRC522 is fully downwards compatible, and can be connected to an F/S mode I2C-bus system. As no master code will be transmitted in such a configuration, the device stays in F/S mode and communicates at F/S mode speeds. 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 60 of 109 NXP Semiconductors MFRC522 Contactless Reader IC 11. Analog Interface and Contactless UART 11.1 General The integrated contactless UART supports the external host online with framing and error checking of the protocol requirements up to 848 kbit/s. An external circuit can to be connected to the communication interface pins MFIN/MFOUT to modulate and demodulate the data. The contactless UART handles the protocol requirements for the communication schemes in co-operation with the host. The protocol handling itself generates bit- and byte-oriented framing and handles error detection like Parity and CRC according to the different contactless communication schemes. Remark: The size and the tuning of the antenna and the power supply voltage have an important impact on the achievable operating distance. 11.2 TX Driver The signal delivered on pin TX1 and pin TX2 is the 13.56 MHz energy carrier modulated by an envelope signal. It can be used to drive an antenna directly, using a few passive components for matching and filtering, see Section 24 "Application information". The signal on TX1 and TX2 can be configured by the register TxControlReg, see Section 9.2.2.5 "TxControlReg". The modulation index can be set by adjusting the impedance of the drivers. The impedance of the p-driver can be configured by the registers CWGsPReg and ModGsPReg. The impedance of the n-driver can be configured by the register GsNReg. Furthermore, the modulation index depends on the antenna design and tuning. The register TxModeReg and TxAutoSelReg control the data rate and framing during transmission and the setting of the antenna driver to support the different requirements at the different modes and transfer speeds. Table 145: Settings for TX1 TX1RFEn 0 1 Force 100ASK X 0 0 1 InVTx1 RFON x 0 1 1 InVTx1 RFOFF x x X x Envelope x 0 1 0 1 0 1 TX1 x RF RF RF RF 0 RF_n GSPMos x pMod pCW pMod pCW pMod pCW GSNMos Remarks x nMod nCW nMod nCW nMod nCW not specified if RF is switched off 100% ASK: TX1 pulled to 0, independent of InvTx1RFOff 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 61 of 109 NXP Semiconductors MFRC522 Contactless Reader IC Table 146: Settings for TX2 TX1RFEn 0 1 Force 100ASK x 0 TX2CW x 0 InVTx2 RFON x 0 1 1 1 0 0 1 0 1 1 0 1 InVTx2 RFOFF x x X x x x x x x Envelope x 0 1 0 1 X X 0 1 0 1 X X TX2 x RF RF RF_n RF_n RF RF_n 0 RF 0 RF_n RF RF_n GSPMos x pMod pCW pMod pCW pCW pCW pMod pCW pMod pCW pCW pCW GSNMos Remarks x nMod nCW nMod nCW nCW nCW nMod nCW nMod nCW nCW nCW Gs always CW for TX2CW 100%ASK:Tx2 pulled to 0 (independent of InvTx2RFOn/INVT X2RFOff) not specified if RF is switched off The following abbreviations are used: * * * * * * * * RF: 13.56 MHz clock derived from 27.12 MHz quartz divided by 2 RF_n: inverted 13.56 MHz clock gspmos: Conductance, configuration of the PMOS array gspmos: Conductance, configuration of the NMOS array pCW: PMOS conductance value for continuos wave defined by CWGsP register pMod: PMOS conductance value for modulation defined by ModGsP register nCW: NMOS conductance value for continuos wave defined by CWGsN register nMod: NMOS conductance value for modulation defined by ModGsN register Remark: If only 1 driver is switched on, the values for ModGsN, ModGsP and CWGsN, CWGsP are used for both drivers. 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 62 of 109 NXP Semiconductors MFRC522 Contactless Reader IC 11.3 Serial Data Switch Two main blocks are implemented in the MFRC522. A digital circuitry, comprising state machines, coder and decoder logic and an analog circuitry with the modulator and antenna drivers, receiver and amplification circuitry. For example, the interface between these two blocks can be configured in the way, that the interfacing signals may be routed to the pins MFIN and MFOUT. This topology supports, that the analog part of the MFRC522 may be connected to the digital part of another device. The serial signal switch is controlled by the register TxSelReg and RxSelReg. The following figure shows the serial data switch for TX1 and TX2. DriverSel internal Coder invert if InvMod=1 Envelope Tristate 1 00 01 10 11 To driver TX1 and TX2 0 = impedance = MOD 1 = inpedance = CW MFIN invert if PolMfin =0 Fig 20. Serial data switch for TX1 and TX2. 11.4 MFIN/MFOUT interface support The MFRC522 is basically divided into digital circuitry and analog circuitry. The digital circuitry contains state machines, coder and decoder logic and so on and the analog circuitry contains the modulator and antenna drivers, receiver and amplification circuitry. The interface between these two blocks can be configured in the way, that the interfacing signals may be routed to the pins MFIN and MFOUT (see Figure 21 "Overview MFIN/MFOUT Signal Routing"). The configuration is done by bits MFOutSel, DriverSel and UARTSel of registers TxSelReg and RxSelReg. This topology supports, that some parts of the analog part of the MFRC522 may be connected to the digital part of another device. The switch MFOutSel in register TxSelReg can be used to measure MIFARE(R) and ISO/IEC14443 related signals. This is especially important during the design In phase or for test purposes to check the transmitted and received data. However, the most important use of MFIN/MFOUT pins is the active antenna concept. An external active antenna circuit can be connected to the digital circuit of the MFRC522. MFOutSel has to be configured in that way that the signal of the internal Miller Coder is send to MFOUT pin (MFOutSel = 4). UARTSel has to be configured to receive Manchester signal with sub-carrier from MFIN pin (UARTSel = 1). It is possible, to connect a 'passive antenna' to pins TX1, TX2 and RX (via the appropriate filter and matching circuit) and at the same time an Active Antenna to the pins MFOUT and MFIN. In this configuration, two RF-parts may be driven (one after another) by one host processor. 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 63 of 109 NXP Semiconductors MFRC522 Contactless Reader IC Remark: The MFRC522 has an extra supply pin (SVDD and PVSS as Ground line) for the MFIN and MFOUT pads. If MFIN pin is not used it should be connected to SVDD or PVSS. If SVDD pin is not used it should be connected to DVDD or PVDD or any other voltage supply pin. M FO UT 0 Tx Bit Stream M iller C oder TS 0 1 TestBus internal Serial data stream Tx 1 2 3 M FO ut Envelop from MFIN 4 5 6 7 TS 0 1 M odulator D river Envelop 2 D river Sel 3 TX2 TX1 Sel 1 Digital Part M FRC522 R FU Serial data stream R x Analog Part M FRC 522 0 0 R x Bit Stream M anchester D ecoder U AR T Sel 1 Sub-carrier D em odulator D em odulator internal 2 M anchester w sub-carrier 3 N R Z coding w /o subcarrier (> 106 kbps) RX M FIN Fig 21. Overview MFIN/MFOUT Signal Routing 11.5 CRC co-processor The following parameters of the CRC co-processor can be configured. The CRC preset value can either be 0000h, 6363h, A671h or FFFFh depending on the bits CRCPreset in register ModeReg. The CRC polynomial for the 16-bit CRC is fixed to x16 + x12 + x5 + 1. The register CRCResultReg indicates the result of the CRC calculation. This register is split into two 8-bit registers indicating the higher and lower byte. The bit MSBFirst in the register ModeReg indicates that data will be loaded with MSB first. Table 147: CRC co-processor parameters Parameter CRC Register Length CRC Algorithm CRC Preset Value Value 16 bit CRC Algorithm according ISO/IEC 14443A and CCITT 0000h, 6363h,A671h or FFFFh depending on the CRCPresetReg register settings 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 64 of 109 NXP Semiconductors MFRC522 Contactless Reader IC 12. FIFO Buffer 12.1 Overview An 64 x 8-bit FIFO buffer is implemented in the MFRC522. It buffers the input and output data stream between the host and the internal state machine of the MFRC522. Thus, it is possible to handle data streams with lengths of up to 64 bytes without taking timing constraints into account. 12.2 Accessing the FIFO Buffer The FIFO-buffer input and output data bus is connected to the register FIFODataReg. Writing to this register stores one byte in the FIFO-buffer and increments the internal FIFO-buffer write-pointer. Reading from this register shows the FIFO-buffer contents stored at the FIFO-buffer read-pointer and decrements the FIFO-buffer read-pointer. The distance between the write- and read-pointer can be obtained by reading the register FIFOLevelReg. When the -Controller starts a command, the MFRC522 may, while the command is in progress, access the FIFO-buffer according to that command. Physically only one FIFO-buffer is implemented, which can be used in input- and output direction. Therefore the -Controller has to take care, not to access the FIFO-buffer in an unintended way. 12.3 Controlling the FIFO-Buffer Besides writing to and reading from the FIFO-buffer, the FIFO-buffer pointers might be reset by setting the bit FlushBuffer in the register FIFOLevelReg to 1. Consequently, the FIFOLevel bits are set to logic 0, the bit BufferOvfl in the register ErrorReg is cleared, the actually stored bytes are not accessible any more and the FIFO-buffer can be filled with another 64 bytes again. 12.4 Status Information about the FIFO-Buffer The host may obtain the following data about the FIFO-buffers status: * Number of bytes already stored in the FIFO-buffer: FIFOLevel in register FIFOLevelReg * Warning, that the FIFO-buffer is almost full: HiAlert in register Status1Reg * Warning, that the FIFO-buffer is almost empty: LoAlert in register Status1Reg * Indication, that bytes were written to the FIFO-buffer although it was already full: BufferOvfl in register ErrorReg. BufferOvfl can be cleared only by setting bit FlushBuffer in the register FIFOLevelReg. The MFRC522 can generate an interrupt signal * If LoAlertIEn in register CommIEnReg is set to logic 1 it will activate pin IRQ when LoAlert in the register Status1Reg changes to 1. * If HiAlertIEN in register CommIEnReg is set to logic 1 it will activate pin IRQ when HiAlert in the register Status1Reg changes to 1. 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 65 of 109 NXP Semiconductors MFRC522 Contactless Reader IC The bit HiAlert is set to logic 1 if maximum WaterLevel bytes (as set in register WaterLevelReg) or less can be stored in the FIFO-buffer. It is generated according to the following equation: HiAlert = ( 64 - FIFOLength ) WaterLevel The bit LoAlert is set to logic 1 if WaterLevel bytes (as set in register WaterLevelReg) or less are actually stored in the FIFO-buffer. It is generated according to the following equation: LoAlert = FIFOLength WaterLevel 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 66 of 109 NXP Semiconductors MFRC522 Contactless Reader IC 13. Timer Unit A timer unit is implemented in the MFRC522. The external host may use this timer to manage timing relevant tasks. The timer unit may be used in one of the following configurations: * * * * * Time-out counter Watch-dog counter Stop watch Programmable one-shot Periodical trigger The timer unit can be used to measure the time interval between two events or to indicate that a specific event occurred after a specific time. The timer can be triggered by events which will be explained in the following, but the timer itself does not influence any internal event (e.g. A time-out during data reception does not influence the reception process automatically). Furthermore, several timer related bits are set and these bits can be used to generate an interrupt. The timer has an input clock of 6.78 MHz (derived from the 27.12 MHz quartz). The timer consists of two stages: 1 prescaler and 1 counter. The prescaler is a 12 bit counter. The reload value for TPrescaler can be defined between 0 and 4095 in register TModeReg and TPrescalerReg. The reload value for the counter is defined by 16 bits in a range of 0 to 65535 in the register TReloadReg. The current value of the timer is indicated by the register TCounterValReg. If the counter reaches 0 an interrupt will be generated automatically indicated by setting the TimerIRq bit in the register CommonIRqReg. If enabled, this event can be indicated on the IRQ line. The bit TimerIRq can be set and reset by the host. Depending on the configuration the timer will stop at 0 or restart with the value in register TReloadReg. The status of the timer is indicated by bit TRunning in register Status1Reg. The timer can be manually started by TStartNow in register ControlReg or manually stopped by TStopNow in register ControlReg. Furthermore the timer can be activated automatically by setting the bit TAuto in the register TModeReg to fulfil dedicated protocol requirements automatically. The time delay of a timer stage is the reload value +1. Maximum time: TPrescaler = 4095, TReloadVal = 65535 => 4096 x 65536/6.78 MHz = 39.59 s Example: To indicate 100 us it is required to count 678 clock cycles. This means the value for TPrescaler has to be set to TPrescaler = 677.The timer has now an input clock of 100 us. The timer can count up to 65535 timeslots of each 100 us. 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 67 of 109 NXP Semiconductors MFRC522 Contactless Reader IC 14. Interrupt Request System The MFRC522 indicates certain events by setting bit IRq in the register Status1Reg and additionally, if activated, by pin IRQ. The signal on pin IRQ may be used to interrupt the host using its interrupt handling capabilities. This allows the implementation of efficient host software. The following table shows the available interrupt bits, the corresponding source and the condition for its activation. The interrupt bit TimerIRq in register CommIRqReg indicates an interrupt set by the timer unit. The setting is done when the timer decrements from 1 down to 0. The TxIRq bit in register CommIRqReg indicates that the transmitter has finished. If the state changes from sending data to transmitting the end of the frame pattern, the transmitter unit sets the interrupt bit automatically. The CRC coprocessor sets the bit CRCIRq in the register DivIRqReg after having processed all data from the FIFO buffer. This is indicated by the bit CRCReady = 1. The bit RxIRq in register CommIRqReg indicates an interrupt when the end of the received data is detected. The bit IdleIRq in register CommIRqReg is set if a command finishes and the content of the command register changes to idle. The bit HiAlertIRq in register CommIRqReg is set to logic 1 if the HiAlert bit is set to logic 1, that means the FIFO buffer has reached the level indicated by the bit WaterLevel. The bit LoAlertIRq in register CommIRqReg is set to logic 1 if the LoAlert bit is set to logic 1, that means the FIFO buffer has reached the level indicated by the bit WaterLevel. The bit ErrIRq in register CommIRqReg indicates an error detected by the contactless UART during sending or receiving. This is indicated by any bit set to logic 1 in register ErrorReg. Table 148: Interrupt Sources Interrupt bit TimerIRq TxIRq CRCIRq RxIRq IdleIRq HiAlertIRq LoAlertIRq ErrIRq Interrupt Source Timer Unit Transmitter CRC co-processor Receiver Command Register FIFO-buffer FIFO-buffer contactless UART Is set automatically, when the timer counts from 1 to 0 a transmitted data stream ends all data from the FIFO buffer has been processed a received data stream ends a command execution finishes the FIFO-buffer is getting full the FIFO-buffer is getting empty an error is detected 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 68 of 109 NXP Semiconductors MFRC522 Contactless Reader IC 15. Oscillator Circuitry The clock applied to the MFRC522 acts as time basis for the coder and decoder of the synchronous system. Therefore stability of the clock frequency is an important factor for proper performance. To obtain highest performance, clock jitter has to be as small as possible. This is best achieved by using the internal oscillator buffer with the recommended circuitry. If an external clock source is used, the clock signal has to be applied to pin OSCIN. In this case special care for clock duty cycle and clock jitter is needed and the clock quality has to be verified. RC522 OSC OUT OSCIN 27.12 MHz Fig 22. Ouartz Connection 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 69 of 109 NXP Semiconductors MFRC522 Contactless Reader IC 16. Power Reduction modes 16.1 Hard Power-down A Hard Power-down is enabled with LOW level on pin NRSTPD. This turns off all internal current sinks as well as the oscillator. All digital input buffers are separated from the input pads and clamped internally (except pin NRSTPD itself). The output pins are frozen at a certain value. 16.2 Soft Power-down The Soft Power-down mode is entered immediately after setting the bit PowerDown in the register CommandReg to 1. All internal current sinks are switched off (including the oscillator buffer). In opposition to the Hard Power-down mode, the digital input-buffers are not separated by the input pads and keep their functionality. The digital output pins do not change their state. During Soft Power-down, all registers values, the FIFO's content and the configuration itself will keep its current content. After setting bit PowerDown in the register CommandReg to 0 it takes 1024 clocks until the Soft Power-down mode is left as indicated by the PoweDown bit itself. Setting it to logic 0 does not immediately clear it. It is cleared automatically by the MFRC522 when the Soft Power-down mode is left. Remark: If the internal oscillator is used, you have to take into account that it is supplied by AVDD and it will take a certain time tosc until the oscillator is stable and the clock cycles can be detected by the internal logic. For the serial UART it is recommended to send the value 55 (hex) to the MFRC522 first. For further access to the registers the oscillator must be stable. Therefore, perform a read accesses to address 0 till the MFRC522 answers to the last read command with the register content of address 0. This indicates that the MFRC522 is active for further operation. 16.3 Transmitter Power-down The Transmitter Power-down mode switches off the internal antenna drivers to turn off the RF field by setting either Tx1RfEn or TX2RFEn in the register TXControlReg to logic 0. 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 70 of 109 NXP Semiconductors MFRC522 Contactless Reader IC 17. Reset and Oscillator Startup Time 17.1 Reset Timing Requirements The reset signal is filtered by a hysteresis circuit and a spike filter (rejects signals shorter than 10 ns) before it enters the digital circuit. In order to perform a reset, the signal has to be low for at least 100 ns. 17.2 Oscillator Startup Time Having set the MFRC522 to a Power-down mode or supplying the IC with XVDD the following figure describes the startup timing for the oscillator. The time tstartup defines the startup time of crystal oscillator circuit. The crystal oscillator startup time is defined by the crystal itself. The tdelay defines the internal delay time of the MFRC522 when the clock signal is stable before the MFRC522 can be addressed. The delay time is calculated as follows: tdelay [s] = 1024/27.12 = 37.76 s. The time tosc is defined as the sum of the time tdelay and tstartup. Device Activation Oscillator Clock Stable Clock Ready t startup t osc t delay t Fig 23. Oscillator Startup time. 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 71 of 109 NXP Semiconductors MFRC522 Contactless Reader IC 18. MFRC522 Command Set 18.1 General Description The behavior is determined by a state machine capable to perform a certain set of commands. By writing the according command-code to register CommandReg the command is executed. Arguments and/or data necessary to process a command are exchanged via the FIFO buffer. 18.2 General Behavior * Each command, that needs a data stream (or data byte stream) as input will immediately process the data it finds in the FIFO buffer. An exception to this rule is the Transceive command. Using this command the transmission is started with the StartSend bit in the BitFramingReg register. * Each command that needs a certain number of arguments will start processing only when it has received the correct number of arguments via the FIFO buffer. * The FIFO buffer is not cleared automatically at command start. Therefore, it is also possible to write the command arguments and/or the data bytes into the FIFO buffer and start the command afterwards. * Each command may be interrupted by the host by writing a new command code into register CommandReg e.g.: the Idle-Command. 18.3 MFRC522 Commands Overview Table 149: Command overview Command Idle Mem Generate RandomID CalcCRC Transmit NoCmd Change Receive Transceive MFAuthent Soft Reset Command code 0000 0001 0010 0011 0100 0111 Action No action; cancels current command execution. Stores 25 byte into the internal buffer Generates a 10 byte random ID number Activates the CRC co-processor or performs a selftest. Transmits data from the FIFO buffer. No command change. This command can be used to modify different bits in the command register without touching the command. E.g. Power-down. Activates the receiver circuitry. Transmits data from FIFO buffer to the antenna and activates automatically the receiver after transmission. Reserved for further use Performs the MIFARE(R) standard authentication as a reader Resets the MFRC522 1000 1100 1101 1110 1111 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 72 of 109 NXP Semiconductors MFRC522 Contactless Reader IC 18.3.1 MFRC522 Command Description 18.3.1.1 Idle Command The MFRC522 is in Idle mode. This command is also used to terminate the actual command. 18.3.1.2 Mem Command Transfers 25 byte from the FIFO to the internal buffer. To read out the 25 byte from the internal buffer, the command Mem with an empty FIFO buffer has to be started. In this case the 25 bytes are transferred from the internal buffer to the FIFO. During a hard power down (reset pin) the 25 byte in the internal buffer remains unchanged but will be lost when supply power is removed from MFRC522. This command terminates automatically when finished and the active command is idle. 18.3.1.3 Generate RandomID Command This command generates a 10 byte random number stored in the internal buffer and overwrites the 10 bytes internal 25 byte buffer. This command terminates automatically when finished and the MFRC522 returns to idle. 18.3.1.4 CalcCRC Command The content of the FIFO is transferred to the CRC co-processor and a CRC calculation is started. The result of this calculation is stored in the CRCResultReg register. The CRC calculation is not limited to a dedicated number of bytes. The calculation is not stopped, when the FIFO gets empty during the data stream. The next byte written to the FIFO is added to the calculation. The pre-set value of the CRC is controlled by the CRCPreset bits of the ModeReg register and the value is loaded to the CRC co-processor when the command is started. This command has to be terminated by writing any command to register CommandReg e.g. the command Idle. If the SelfTest bits in the register AutoTestReg are set correct, the MFRC522 is in Self Test mode and starting the CalCCRC command performs a digital selftest. The result of the selftest is written to the FIFO. 18.3.1.5 Transmit Command The content of the FIFO is transmitted immediately after starting the command. Before transmitting the FIFO content all relevant register have to be set to transmit data. This command terminates automatically when the FIFO gets empty. It can be terminated by any other command written to the command register. 18.3.1.6 NoCmdChange Command This command does not influence any ongoing command in the CommandReg register. It can be used to manipulate any bit except the command bits in the CommandReg register, e.g. the bits RcvOff or PowerDown. 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 73 of 109 NXP Semiconductors MFRC522 Contactless Reader IC 18.3.1.7 Receive Command The MFRC522activates the receiver path and waits for any data stream to be received. The correct settings have to be chosen before starting this command. This command terminates automatically when the received data stream ends. This is indicated either by the end of frame pattern or by the length byte depending on the selected framing and speed. Remark: If the bit RxMultiple in the RxModeReg register is set to logic 1, the Receive command does not terminate automatically. It has to be terminated by activating any other command in the CommandReg register. 18.3.1.8 Transceive Command This circular command repeats transmitting data from the FIFO and receiving data from the RF field continuously. The first action is transmitting and after a transmission the command is changed to receive a data stream. Each transmission process has to be started by setting bit StartSend in the register BitFramingReg to logic 1. This command has to be cleared by software by writing any command to register CommandReg e.g. the command idle. Remark: If the bit RxMultiple in register RxModeReg is set to logic 1, this command will never leave the receiving state, because the receiving will not be cancelled automatically. 18.3.1.9 MFAuthent Command This command handles the MIFARE(R) authentication to enable a secure communication to any MIFARE(R) classic card. The following data shall be written to the FIFO before the command can be activated: * * * * * * * * * * * * Authentication command code (60h, 61h) Block address Sector key byte 0 Sector key byte 1 Sector key byte 2 Sector key byte 3 Sector key byte 4 Sector key byte 5 Card serial number byte 0 Card serial number byte 1 Card serial number byte 2 Card serial number byte 3 In total 12 bytes shall be written to the FIFO. Remark: When the MFAuthent command is active, any FIFO access is blocked. Anyhow if there is an access to the FIFO, the bit WrErr in the ErrorReg register is set. 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 74 of 109 NXP Semiconductors MFRC522 Contactless Reader IC This command terminates automatically when the MIFARE(R) card is authenticated and the bit MFCrypto1On in the Status2Reg register is set to logic 1. This command does not terminate automatically when the card does not answer, therefore the timer should be initialized to automatic mode. In this case, beside the bit IdleIrq, the bit TimerIrq can be used as termination criteria. During authentication processing the bit RxIrq and bit TxIrq are blocked. The Crypto1On bit is only valid after termination of the authent command (either after processing the protocol or after writing IDLE to the command register). In case there is an error during authentication, the bit ProtocolErr in the ErrorReg register is set to logic 1 and the bit Crypto1On in register Status2Reg is set to logic 0. 18.3.1.10 SoftReset Command This command performs a reset of the device. The configuration data of the internal buffer remains unchanged. All registers are set to the reset values. This command terminates automatically when finished. Remark: The SerialSpeedReg register is reset and therefore the serial data rate is set to 9.6 kbps. 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 75 of 109 NXP Semiconductors MFRC522 Contactless Reader IC 19. Testsignals 19.1 Selftest The MFRC522 has the capability to perform a digital selftest. To start the selftest the following procedure has to be performed: 1. Perform a soft reset. 2. Clear the internal buffer by writing 25 bytes of 00h and perform the Config Command. 3. Enable the Selftest by writing the value 09h to the register AutoTestReg. 4. Write 00h to the FIFO. 5. Start the Selftest with the CalcCRC Command. 6. The Selftest will be performed. 7. When the Selftest is finished, the FIFO contains the following bytes: Correct answer for register VersionReg equal to 90h: 00h, BFh, 7Fh, 47h, 75h, 32h, B4h, 35h, 87h, 22h, E3h, 9Ah, 5Ah, FFh, 4Ah, 96h, 98h, 30h, 4Eh, 37h, EDh, 58h, 59h, 98h, 0fh, 49h, 03h, 61h, 04h, 3Bh, 5Bh, 9Eh, 49h, 59h, 5Ch, E7h, 3Dh, 7Ch, FDh, 4Fh, FFh, 63h, 4Eh, E 2h, 02h, E9h, U9h, 30h, 07h, ADh, 49h, C6h, 4Bh, 00h, 29h, 32h, 19h CAh 50h 2Eh 78h 94h DFh 8Dh Correct answer for register VersionReg equal to 91h: 00h, C2h, 10h, 14h, 64h, 22h, 1Fh, D9h, C6h, D8h, E6h, AFh, 22h, BCh, A7h, 0Fh, 37h, 7Ch, D2h, 30h, 72h, D3h, F3h, B5h, D5h, 4Dh, AAh, 61h, B5h, 72h, 53h, 5Eh, 32h, D9h, 5Eh, C9h, BDh, 35h, 14h, 25h, B7h, 70h, A1h, 70h, 65h, CDh, DEh, 1Dh, 57h, C7h, 3Eh, DBh, F4h, AAh, 7Eh, 29h, 5Ch, 73h, 5Ah, 2Eh, ECh, 41h, 02h, 79h 19.2 Test bus The test bus is implemented for production test purposes. The following configuration can be used to improve the design of a system using the MFRC522. The test bus allows to route internal signals to the digital interface. The test bus signals are selected by accessing TestBusSel in register TestSel2Reg. Table 150: TestSel2Reg register (address 07h) Pins Testsignal D6 sdata D5 scoll D4 svalid D3 sover D2 RCV_reset D1 - 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 76 of 109 NXP Semiconductors MFRC522 Contactless Reader IC Table 151: Description of Testsignals Pins D6 D5 D4 D3 D2 D1 Testsignal sdata scoll svalid sover RCV_reset Description shows the actual received data stream. shows if in the actual bit a collision has been detected (106 kbit/s only) shows if sdata and scoll are valid shows that the receiver has detected a stop condition shows if the receiver is reset reserved Table 152: TestSel2Reg register (address 0Dh) Pins Testsignal D6 clkstable D5 clk27/8 D4 D3 D2 clk27 D1 - Table 153: Description of Testsignals Pins D6 D5 D4 to D3 D2 D1 Testsignal clkstable clk27/8 clk27 Description shows if the oscillator delivers a stable signal. shows the output signal of the oscillator divided by 8 reserved shows the output signal of the oscillator reserved 19.3 Testsignals at pin AUX With the MFRC522, the user may select internal signals to measure them at pin AUX. These measurements can be helpful during the design-in phase to optimise the design or for test purpose. Table 154 shows an overview of the signal that can be switched to pin AUX1 or AUX2 by setting SelAux1 or SelAux2 in the register AnalogTestReg. Please also refer to register AnalogSelAux. Remark: The DAC has a current output. It is recommended to use a 1 k pull-down resistance at pins AUX1/AUX2. Table 154: Testsignals description SelAux 0000 0001 0010 0011 0100 0101 0110 0111 - 1001 1010 1011 112132 Description for Aux1 / Aux2 Tristate DAC: register TestDAC 1/2 DAC: testsignal corr1 Reserved DAC: testsignal MinLevel DAC: ADC_I DAC: ADC_Q Reserved High low (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 77 of 109 NXP Semiconductors MFRC522 Contactless Reader IC Table 154: Testsignals description SelAux 1100 1101 1110 1111 Description for Aux1 / Aux2 TxActive RxActive Subcarrier detected TstBusBit 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 78 of 109 NXP Semiconductors MFRC522 Contactless Reader IC 19.3.1 Example: Output TestDAC 1 on AUX1 and TestDAC 2 on AUX2 Register AnalogTestReg is set to 11h. The output of AUX1 corresponds to the TestDAC 1 and the output of AUX2 to the TestDAC 2. The value of TestDAC 1 and TestDAC 2 is controlled by register TestDAC1Reg and TestDAC2Reg. Figure 24 shows TestDAC1Reg programmed with a slope from 00h to 3Fh. TestDAC2Reg has been programmed with a rectangular signal with values of 00h and 3Fh. Fig 24. Output TestDAC 1 on AUX1 and TestDAC 2 on AUX2 19.3.2 Example: Output Testsignal Corr1 on AUX1 and MinLevel on AUX2 The following Figure 25 shows the test signal Corr 1 and the test signal MinLevel. The AnalogTestReg is set to 24h. The output of AUX1 corresponds to the Corr1 signal and AUX2 to the MinLevel. 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 79 of 109 NXP Semiconductors MFRC522 Contactless Reader IC Fig 25. Output Testsignal Corr1 on AUX1 and MinLevel on AUX2. 19.3.3 Example: Output ADC channel I on AUX 1 and ADC channel Q on AUX 2 Figure 26 shows the ADC_I and ADC_Q channel behaviour. The AnalogTestReg is set to 56h. Fig 26. Output ADC channel I on AUX 1 and ADC channel Q on AUX 2. 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 80 of 109 NXP Semiconductors MFRC522 Contactless Reader IC 19.3.4 Example: Output RxActive on AUX 1 and TxActive on AUX 2 The following Figure 27 shows the RXActive and TXActive signal in accordance to the RF communication. The AnalogTestReg was set to CDh. Remark: At 106 kbit/s, RxActive is HIGH during databits, parity and CRC reception. Startbits are not included. At 106 kbit/s, TxActive is HIGH during startbits, databits, parity and CRC transmission. At 212, 424 and 848 kbit/s, RxActive is HIGH during datbits and CRC reseption. Startbits are not included. At 212, 424 and 848 kbit/s, TxActive is HIGH during databits and CRC transmission. Fig 27. Output RxActive on AUX 1 and TxActive on AUX 2. 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 81 of 109 NXP Semiconductors MFRC522 Contactless Reader IC 19.3.5 Example: Output Rx Data Stream on AUX 1 and AUX 2 The following Figure 28 shows the actual received data stream. TestSel2Reg is set to 07h to enable certain digital test data on D1-D6 (see Section 19.2 "Test bus"). The register TestSel1Reg is set to 06h (D6 = sdata) and AnalogTestReg is set to FFh to output the received data stream to pin AUX1 and AUX2. Fig 28. Output Rx data stream on AUX 1 and AUX 2. 19.4 PRBS (Pseudo-Random Binary Sequence) Enables the PRBS9 or PRBS15 sequence according to ITU-TO150. To start the transmission of the defined datastream the command TRANSMIT has to be activated. The preamble/Sync byte/start bit/parity bit are generated automatically depending on the selected mode. Remark: All relevant register to transmit data have to be configured before entering PRBS mode according ITU-TO150. 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 82 of 109 NXP Semiconductors MFRC522 Contactless Reader IC 20. Limiting values Table 155. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol AVDD DVDD PVDD TVDD SVDD Vin Vin,MFIN Ptot TJ ESDH ESDM Input voltage Input voltage Total power dissipation per package (VBUS and DVDD in short cut mode) Junction temperature range ESD Susceptibility (Human Body model) 1500 , 100 pF; JESD22-A114-B ESD Susceptibility (Machine model) 0.75 H, 200 pF; JESD22-A114-A for all input-pins except MFIN and Rx for MFIN pin only PVSS -0.5 PVDD +0.5 V PVSS-0.5 SVDD+0.5 200 100 2000 200 V mW C V V Parameter Supply voltage Conditions Min -0.5 Max +4.0 Unit V 21. Recommended operating conditions Table 156: Operating conditions Symbol Parameter Tamb AVDD DVDD TVDD PVDD [1] [2] [3] Conditions HVQFN32 AVSS = DVSS = PVSS= TVS = 0 V, PVDD AVDD = DVDD =TVDD [2] Min -25 2.5 Typ 3.3 Max +85 3.6 Unit C V Ambient Temperature Supply Voltage [3] 1.6 1.8 3.6 V Supply voltages below 3 V reduces the performance (e.g. the achievable operating distance). AVDD, DVDD and TVDD shall always be on the same voltage level. PVDD shall always be on the same or lower voltage level than DVDD. 22. Thermal characteristics Table 157: Thermal characteristics Symbol Rthj-a Parameter Conditions Package Typ Unit K/W Thermal resistance from In still air with exposed junction to ambient pad soldered on a 4 layer Jedec PCB HVQFN32 40 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 83 of 109 NXP Semiconductors MFRC522 Contactless Reader IC 23. Characteristics 23.1 Input Pin Characteristics 23.1.1 Input Pin characteristics for pins EA, I2C and NRESET Table 158: Input Pin characteristics for pins EA, I2C and NRESET Symbol ILeak VIH VIL Parameter Input Leakage current Input voltage High Input voltage Low Conditions Min -1 Typ Max 1 Unit A V 0.7 PVDD - 0.3 PVDD V 23.1.2 Input Pin characteristics for pin MFIN Table 159: Input Pin characteristics for MFIN Symbol ILeak VIH VIL Parameter Input Leakage current Input voltage High Input voltage Low Conditions Min -1 Typ Max 1 Unit A V 0.7 SVDD - 0.3 SVDD V 23.1.3 Input/Output Pin characteristics for pins D1, D2, D3, D4, D5, D6 and D7 Table 160: Input/Output Pin characteristics for pins D1, D2, D3, D4, D5, D6 and D7 Symbol Parameter ILeak VIH VIL VOH VOL IOH IOL Input Leakage current Input voltage High Input voltage Low Output voltage HIGH PVDD = 3 V, IO = 4 mA Output voltage LOW PVDD = 3 V, IO = 4 mA Output current drive HIGH Output current drive LOW PVDD = 3 V PVDD = 3 V Conditions Min -1 0.7 PVDD Typ Max 1 0.3 PVDD PVDD Unit A V V V PVDD -400 mV PVSS - PVSS +400 mV V 4 4 mA mA 23.1.4 Input Pin characteristics for pin SDA Table 161: Input Pin characteristics for pin SDA Symbol Parameter ILeak VIH VIL Input Leakage current Input voltage High Input voltage Low Conditions Min -1 0.7 PVDD Typ Max 1 0.3 PVDD Unit A V V 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 84 of 109 NXP Semiconductors MFRC522 Contactless Reader IC 23.1.5 Output Pin characteristics for Pin MFOUT Table 162: Output Pin characteristics for Pin MFOUT Symbol Parameter VOH VOL IOL IOH Conditions Min Typ Max SVDD Unit V Output voltage HIGH SVDD = 3 V, IO = 4 mA Output voltage LOW Output current drive LOW Output current drive HIGH SVDD = 3 V, IO = 4 mA SVDD = 3 V SVDD = 3 V SVDD -400 mV SVSS - PVSS +400 mV V 4 4 mA mA 23.1.6 Output Pin characteristics for Pin IRQ Table 163: Output Pin characteristics for Pin IRQ Symbol Parameter VOH VOL IOL IOH Conditions Min Typ Max PVDD Unit V Output voltage HIGH PVDD = 3 V, IO = 4 mA Output voltage LOW Output current drive LOW Output current drive HIGH PVDD = 3 V, IO = 4 mA PVDD = 3 V PVDD = 3 V PVDD -400 mV PVSS - PVSS +400 mV V 4 4 mA mA 23.1.7 Input Pin characteristics for Pin Rx Table 164: Input Pin characteristics for Pin Rx Symbol Parameter VIN,RX CIN,RX Input voltage range RX Input capacitance AVDD = 3 V, Receiver active, VRX = 1 VPP, 1.5 VDC offset RX Input Series resistance AVDD = 3 V, Receiver active, VRX = 1 VPP, 1.5 VDC offset Conditions Min -1 Typ 10 Max Unit pF AVDD +1 V V RIN,RX - 350 - [1] The voltage on RX in clamped by internal diodes to AVSS and AVDD. 23.1.8 Input Pin characteristics for pin OSCIN Table 165: Input Pin characteristics for OSCIN Symbol ILeak Parameter Input Leakage current Conditions Min -1 Typ Max 1 Unit A 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 85 of 109 NXP Semiconductors MFRC522 Contactless Reader IC Table 165: Input Pin characteristics for OSCIN Symbol VIH VIL COSCIN Parameter Input voltage High Input voltage Low Input capacitance AVDD = 2.8 V, VDC = 0.65 V, VAC = 1 VPP Conditions Min Typ 2 Max Unit V pF 0.7 AVDD - 0.3 AVDD V 23.1.9 Output Pin characteristics for Pins AUX1 and AUX2 Table 166: Output Pin characteristics for Pins AUX1 and AUX2 Symbol Parameter VOH VOL IOL IOH Conditions Min Typ Max DVDD Unit V Output voltage HIGH DVDD = 3 V, IO = 4 mA Output voltage LOW Output current drive LOW Output current drive HIGH DVDD = 3 V, IO = 4 mA DVDD = 3 V DVDD = 3 V DVDD -400 mV DVSS - DVSS +400 mV V 4 4 mA mA 23.1.10 Output Pin characteristics for Pins TX1 and TX2 Table 167: Output Pin characteristics for Pins TX1 and TX2 Symbol VOH,C32,3V Parameter Output voltage HIGH Conditions TVDD = 3 V and ITX = 32 mA, CWGsP = 3Fh TVDD = 3 V and ITX = 80 mA, CWGsP = 3Fh TVDD = 2.5 V and ITX = 32 mA, CWGsP = 3Fh TVDD = 2.5 V and ITX = 80 mA, CWGsP = 3Fh Output voltage LOW TVDD = 3 V and ITX = 32 mA, CWGsP = 0Fh TVDD = 3 V and ITX = 80 mA, CWGsP = 0Fh TVDD = 2.5 V and ITX = 32 mA, CWGsP = 0Fh TVDD = 2.5 V and ITX = 80 mA, CWGsP = 0Fh Min TVDD -150 mV Typ Max Unit mV VOH,C80,3V TVDD -400 mV - - mV VOH,C32,2V5 TVDD -240 mV - - mV VOH,C80,2V5 TVDD -640 mV - - mV VOL,C32,3V - - 150 mV VOL,C80,3V - - 400 mV VOL,C32,2V5 - - 240 mV VOL,C80,2V5 - - 640 mV 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 86 of 109 NXP Semiconductors MFRC522 Contactless Reader IC 23.2 Current Consumption Table 168: Current Consumption Symbol IHPD Parameter Hard Power-down Current Soft Power-down Current Digital Supply Current Analog Supply Current Conditions AVDD = DVDD = TVDD = PVDD = 3 V, NRESET = LOW AVDD = DVDD = TVDD = PVDD = 3 V DVDD = 3 V AVDD = 3 V, bit RCVOff = 0 AVDD = 3 V, bit RCVOff = 1 [2] [4] Min - Typ - Max 5 Unit A ISPD IDVDD IAVDD [4] - 6.5 7 3 10 9 10 5 A mA mA mA IAVDD,RCVOFF Analog Supply Current, receiver switched off IPVDD ITVDD ISVDD [1] [2] [3] [4] [5] [6] Pad Supply Current Transmitter Supply Continuous Wave Current MFIN/MFOUT Pad Supply Current - 60[5] - 40 100 4 mA mA mA [1][3] [6] ITVDD depends on TVDD and the external circuitry connected to Tx1 and Tx2 IPVDD depends on the overall load at the digital pins. During operation with a typical circuitry the overall current is below 100 mA. ISPD and IHPD are the total currents over all supplies. Typical value using a complementary driver configuration and an antenna matched to 40 between TX1 and TX2 at 13.56 MHz ISVDD depends on the load at the MFOUT pin. 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 87 of 109 NXP Semiconductors MFRC522 Contactless Reader IC 23.3 RX Input Voltage Range Table 169: RX Input Voltage Range Symbol Parameter Conditions AVDD = 3 V Min Typ 100 4 Max Unit mVpp Vpp VRX,MinIV,Man Minimum Input voltage, Manchester Coded VRX,MaxIV,Man Maximum Input voltage, AVDD = 3 V Manchester Coded Figure 29 outlines the voltage definitions. Vin,RX Input Voltage Range AVDD+1V Manchester Coded Signals VRXMod,man V RX,IV,man Vmid 13.56MHz carrier 0V -1V Fig 29. RX Input Voltage Range 23.4 RX Input Sensitivity Table 170: RX Input Sensitivity Symbol Parameter Conditions Min Typ 5 Max Unit mV AVDD = 3 V, RxGain = 7 VRXMod,Man Minimum modulation voltage Figure 29 outlines the voltage definitions. 23.5 Clock Frequency Table 171: Clock Frequency Symbol fOSCIN dFEC tjitter Parameter Clock Frequency Duty Cycle of Clock Frequency Jitter of Clock Edges Conditions Min 40 Typ 27.12 50 Max 60 10 Unit MHz % ps, RMS 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 88 of 109 NXP Semiconductors MFRC522 Contactless Reader IC 23.6 XTAL Oscillator Table 172: XTAL Oscillator Symbol Parameter Conditions Min Typ 1.1 0.2 2 2 Max Unit V V pF pF VOH,OSCOUT Output Voltage High XTAL2 VOL,OSCOUT Output Voltage Low XTAL2 CIN,OSCOUT CIN,OSCIN Input capacitance OSCOUT Input capacitance OSCIN 23.7 Typical 27.12 MHz Crystal Requirements Table 173: XTAL Oscillator Symbol fXTAL ESR CL PXTAL Parameter XTAL Frequency Range XTAL Equivalent Series resistance XTAL Load capacitance XTAL Drive Level Conditions Min Typ 27.12 10 50 Max 100 100 Unit MHz pF W 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 89 of 109 NXP Semiconductors MFRC522 Contactless Reader IC 23.8 Timing for the SPI compatible interface Table 174: Timing Specification for SPI Symbol tSCKL tSCKH tSHDX tDXSH tSLDX tSLNH Parameter SCK low pulse width SCK high pulse width SCK high to data changes data changes to SCK high SCK low to data changes SCK low to NSS high Conditions Min 50 50 25 25 0 Typ Max 25 Unit ns ns ns ns ns ns tSCKL tSCKH tSCKL SCK tSLDX tDXSH tSHDX tDXSH MOSI MSB LSB MISO MSB LSB tSLNH NSS Remark: The signal NSS has to be low to be able to send several bytes in one datastream. To send more than one datastream NSS has to be set to HIGH level in between the data streams. Fig 30. Timing Diagram for SPI. 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 90 of 109 NXP Semiconductors MFRC522 Contactless Reader IC 23.9 I2C Timing Table 175. Overview I2C Timing in Fast mode Symbol Parameter fSCL tHD;STA SCL clock frequency Hold time (repeated) START condition. After this period, the first clock pulse is generated Set-up time for a repeated START condition Set-up time for STOP condition LOW period of the SCL clock HIGH period of the SCL clock Data hold time Data set-up time Rise time SCL signals Fall time SCL signals Rise time of both SDA and SCL signals Fall time of both SDA and SCL signals Bus free time between a STOP and START condition Fast mode Min 0 600 Max 400 High speed mode Min 0 160 Max 3400 ns 600 600 1300 600 0 100 20 20 20 20 1.3 900 300 300 300 300 160 160 160 60 0 10 10 10 10 10 1.3 ns ns tLOW tHIGH tHD;DAT tSU;DAT trscl tfscl trsda tfsda tBUF ns ns 70 40 40 80 80 ns ns ns ns ns ns s kHz Unit tSU;STA tSU;STO Fig 31. Timing for F/S mode devices on the I2C-bus. 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 91 of 109 NXP Semiconductors MFRC522 Contactless Reader IC 24. Application information The figure below shows a typical circuit diagram, using a complementary antenna connection to the MFRC522. The antenna tuning and RF part matching is described in the application note Ref. 1 and Ref. 2. supply DVDD PVDD PVSS AVDD TVD D RX R1 VMID Cvmid CRx R2 C1 C0 C0 C2 C2 C1 Ra Antenna NRSTPD TX1 L0 Processor Host Interface RC522 TVSS Ra Lant TX2 IR Q L0 IRQ AVSS OSCIN DVSS OSCOUT 27,12 MHz Fig 32. Typical Application Circuit Diagram 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 92 of 109 NXP Semiconductors MFRC522 Contactless Reader IC 25. Package outline Fig 33. Package outline package version (HVQFN32) Detailed package information can be found on NXP Internet http://www.nxp.com/package/SOT617-1.html 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 93 of 109 NXP Semiconductors MFRC522 Contactless Reader IC 26. Handling information Moisture Sensitivity Level (MSL) Evaluation has been performed according to SNW-FQ-225B rev.04/07/07 (JEDEC J-STD-020C). MSL for this package is level 1 which means 260 C convection reflow temperature. Dry pack is not required. Unlimited out of pack Floor Life at maximum ambient 30 C/85%RH. 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 94 of 109 NXP Semiconductors MFRC522 Contactless Reader IC 27. Packing information Fig 34. Packing Information 1 Tray 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 95 of 109 NXP Semiconductors MFRC522 Contactless Reader IC Fig 35. Packing Information 5Tray 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 96 of 109 NXP Semiconductors MFRC522 Contactless Reader IC 28. Abbreviations Table 176: Abbreviations Acronym ASK PCD PICC PCD AE PICC PICCAE PCD Description Amplitude Shift keying Proximity Coupling Device. Definition for a Card reader/writer according to the ISO/IEC 14443 specification. Proximity Cards. Definition for a contactless Smart Card according to the ISO/IEC 14443 specification. Communication flow between a PCD and a PICC according to the ISO/IEC 14443A/MIFARE(R) Communication flow between a PICC and a PCD according to the ISO/IEC 14443A/MIFARE(R). Modulation Index The modulation index is defined as the voltage ratio (Vmax - Vmin)/ (Vmax + Vmin). Loadmodulation Index The load modulation index is defined as the card's voltage ratio (Vmax - Vmin)/ (Vmax + Vmin) measured at the card's coil. 29. References [1] [2] AN - MFRC52x Reader IC Family Directly Matched Antenna Design -- Application note for Mifare MFRC52x Reader IC Antenna Design AN - Mifare(14443A) 13,56 MHz RFID Proximity Antennas -- Application note for Mifare Proximity Antenna Design 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 97 of 109 NXP Semiconductors MFRC522 Contactless Reader IC 30. Revision history Table 177: Revision history Document ID 112132 Release date Mai 2007 Data sheet status Product datasheet Change notice 200705005F Doc. number Supersedes Revision 3.1 * * * * * * 112131 correction Interface PIN order in Table 135 "Connection Scheme for detecting the different Interface Types" correction Table 137 removed D0 from Table 150, Table 151, Table 152, Table 153 removed 212, 424, 848 kbaud from Table 169 correction typical application circuit diagram Figure 32 add selftest answer for version reg. 91h in Section 19.1 "Selftest" (see CPCN 200705005F) Product datasheet Revision 3.0 Introduction new NXP data sheet layout Add Section 4 "Quick reference data" Characterization up to 848 kbit/s Add notes to Table 3 "Pin description" Correction RFU description in Table 6 "Behavior of Register Bits and its Designation" Correction access rights of bits 6-4 and 2-0 in Table 33 "BitFramingReg register (address 0Dh); reset value: 00h" Correction DTRQ to Output in Table 135 "Connection Scheme for detecting the different Interface Types" Combined "Absolute Maximum Ratings" and "ESD Characteristics" in Section 20 "Limiting values" Renamed Table 161 "Input Pin characteristics for pin SDA" and delete "VOL and IOL" Product data sheet Revision 2.1 Document status changed to product specification Change Ordering Information Chapter 5 Add Handling Information Chapter 26 Add Packing Information Chapter 27 Add Test Signal Examples in Chapter 19.3 Revision 2.0 Preliminary data sheet Revision 1.0 TxSelReg - bit DriverSel - combination 10 Document status chacnged to preliminary specification add package web-link (chapter 25) add ordering information (chapter 5) Objective data sheet Revision 0.4 Document status changed to objective specification changes in various register descriptions SVDD Pin (chapter 7.2) ParityDisable bit (chapter 9.2.1.14) add MFIN / MFOUT description (chapter 11.4) various spelling corrections Revision 0.3 September 2006 * * * * * * * * * 112130 December 2005 * * * * * 112121 112120 September 2005 * * * * 112110 July 2005 July 2005 * * * * * * 112104 November 2004 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 98 of 109 NXP Semiconductors MFRC522 Contactless Reader IC Table 177: Revision history ...continued Document ID Release date Data sheet status Change notice Doc. number Supersedes * * * 112103 temporary remove type ordering information changes in register description adaptation figure 22 changes in register description October 2004 * 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 99 of 109 NXP Semiconductors MFRC522 Contactless Reader IC 31. Legal information 31.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 31.2 Definitions Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 31.3 Disclaimers General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 31.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. MIFARE(R) -- is a registered trademark of NXP B.V. 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 100 of 109 NXP Semiconductors MFRC522 Contactless Reader IC 32. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: sales.addresses@www.nxp.com continued >> 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 101 of 109 NXP Semiconductors MFRC522 Contactless Reader IC Notes continued >> 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 102 of 109 NXP Semiconductors MFRC522 Contactless Reader IC 33. Tables Quick reference data . . . . . . . . . . . . . . . . . 3 Ordering information . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . 7 Communication overview for ISO/IEC 14443A/MIFARE(R) reader/writer . . . . . . . . 9 Table 5: MFRC522 Registers Overview . . . . . . . . 11 Table 6: Behavior of Register Bits and its Designation 13 Table 7: Reserved register (address 00h); reset value: 00h. . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 8: Description of Reserved register bits . . . . 13 Table 9: CommandReg register (address 01h); reset value: 20h. . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 10: Description of CommandReg bits. . . . . . . 14 Table 11: CommIEnReg register (address 02h); reset value: 80h. . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 12: Description of CommIEnReg bits . . . . . . . 14 Table 13: DivIEnReg register (address 03h); reset value: 00h. . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 14: Description of DivIEnReg bits. . . . . . . . . . 16 Table 15: CommIRqReg register (address 04h); reset value: 14h. . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 16: Description of CommIRqReg bits . . . . . . 16 Table 17: DivIRqReg register (address 05h); reset value: X0h . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 18: Description of DivIRqReg bits . . . . . . . . . 17 Table 19: ErrorReg register (address 06h); reset value: 00h. . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 20: Description of ErrorReg bits . . . . . . . . . . . 18 Table 21: Status1Reg register (address 07h); reset value: 21h. . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 22: Description of Status1Reg bits . . . . . . . . . 19 Table 23: Status2Reg register (address 08h); reset value: 00h. . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 24: Description of Status2Reg bits . . . . . . . . . 20 Table 25: FIFODataReg register (address 09h); reset value: XXh . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 26: Description ofFIFODataReg bits. . . . . . . . 21 Table 27: FIFOLevelReg register (address 0Ah); reset value: 00h. . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 28: Description of FIFOLevelReg bits . . . . . . 21 Table 29: WaterLevelReg register (address 0Bh); reset value: 08h . . . . . . . . . . . . . . . . . . . . 21 Table 30: Description of WaterLevelReg bits . . . . . . 22 Table 31: ControlReg register (address 0Ch); reset value: 10h. . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 32: Description of ControlReg bits . . . . . . . . . 22 Table 1. Table 2: Table 3: Table 4: Table 33: BitFramingReg register (address 0Dh); reset value: 00h . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 34: Description of BitFramingReg bits . . . . . . 23 Table 35: CollReg register (address 0Eh); reset value: XXh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 36: Description of CollReg bits. . . . . . . . . . . . 23 Table 37: Reserved register (address 0Fh); reset value: 00h . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 38: Description of Reserved register bits . . . . 24 Table 39: Reserved register (address 10h); reset value: 00h . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 40: Description of Reserved register bits . . . . 24 Table 41: ModeReg register (address 11h); reset value: 3Fh . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 42: Description of ModeReg bits . . . . . . . . . . 25 Table 43: TxModeReg register (address 12h); reset value: 00h . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 44: Description of TxModeReg bits . . . . . . . . 26 Table 45: RxModeReg register (address 13h); reset value: 00h . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 46: Description of RxModeReg bits . . . . . . . . 26 Table 47: TxControlReg register (address 14h); reset value: 80h . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 48: Description of TxControlReg bits . . . . . . . 27 Table 49: TxAutoReg register (address 15h); reset value: 00h . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 50: Description of TxAutoReg bits . . . . . . . . . 28 Table 51: TxSelReg register (address 16h); reset value: 10h . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 52: Description of TxSelReg bits . . . . . . . . . . 28 Table 53: RxSelReg register (address 17h); reset value: 84h . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 54: Description of RxSelReg bits . . . . . . . . . . 29 Table 55: RxThresholdReg register (address 18h); reset value: 84h . . . . . . . . . . . . . . . . . . . . 30 Table 56: Description of RxThresholdReg bits. . . . . 30 Table 57: DemodReg register (address 19h); reset value: 4Dh . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 58: Description of DemodReg bits . . . . . . . . . 30 Table 59: Reserved register (address 1Ah); reset value: 00h . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 60: Description of Reserved register bits . . . . 31 Table 61: Reserved register (address 1Bh); reset value: 00h . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 62: Description of Reserved register bits . . . . 31 Table 63: MfTxReg register (address 1Ch); reset value: 62h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 continued >> 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 103 of 109 NXP Semiconductors MFRC522 Contactless Reader IC Table 98: Description of lower TReloadReg bits . . . 38 Table 99: TCounterValReg (Higher bits) register (address 2Eh); reset value: XXh . . . . . . . 39 Table 100:Description of higher TCounterValReg bits. 39 Table 101:TCounterValReg (Lower bits) register (address 2Fh); reset value: XXh . . . . . . . 39 Table 102:Description of lower TCounterValReg bits . 39 Table 103:Reserved register (address 30h); reset value: 00h . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 104:Description of Reserved register bits . . . 39 Table 105:TestSel1Reg register (address 31h); reset value: 00h . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 106:Description of TestSel1Reg bits . . . . . . . 40 Table 107: TestSel2Reg register (address 32h); reset value: 00h . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 108:Description of TestSel2Reg bits . . . . . . . 40 Table 109:TestPinEnReg register (address 33h); reset value: 80h . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 110:Description of TestPinEnReg bits . . . . . . 41 Table 111: TestPinValueReg register (address 34h); reset value: 00h . . . . . . . . . . . . . . . . . . . . 41 Table 112:Description of TestPinValueReg bits . . . . 41 Table 113: TestBusReg register (address 35h); reset value: XXh . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 114:Description of TestBusReg bits . . . . . . . . 42 Table 115: AutoTestReg register (address 36h); reset value: 40h . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 116:Description of AutoTestReg bits . . . . . . . 42 Table 117: VersionReg register (address 37h); reset value: XXh . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 118:Description of VersionReg bits . . . . . . . . 42 Table 119: AnalogTestReg register (address 38h); reset value: 00h . . . . . . . . . . . . . . . . . . . . 43 Table 120:Description of AnalogTestReg bits . . . . . 43 Table 121: TestDAC1Reg register (address 39h); reset value: XXh . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 122:Description of TestDAC1Reg bits . . . . . . 44 Table 123:TestDAC2Reg register (address 3Ah); reset value: XXh . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 124:Description ofTestDAC2Reg bits . . . . . . 44 Table 125: TestADCReg register (address 3Bh); reset value: XXh . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 126:Description of TestADCReg bits . . . . . . . 44 Table 127: Reserved register (address 3Ch); reset value: FFh . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 128:Description of Reserved register bits . . . 45 Table 129:Reserved register (address 3Dh); reset value: 00h . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 130:Description of Reserved register bits . . . 45 continued >> Table 64: Description of MifNFCReg bits . . . . . . . . . 31 Table 65: MfRxReg register (address 1Dh); reset value: 00h. . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 66: Description of ManualRCVReg bits . . . . . 32 Table 67: Reserved register (address 1Eh); reset value: 00h. . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 68: Description of Reserved register bits . . . . 32 Table 69: SerialSpeedReg register (address 1Fh); reset value: EBh . . . . . . . . . . . . . . . . . . . . 32 Table 70: Description of SerialSpeedReg bits . . . . . 32 Table 71: Reserved register (address 20h); reset value: 00h. . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 72: Description of Reserved register bits . . . . 33 Table 73: CRCResultReg register (address 21h); reset value: FFh . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 74: Description of CRCResultReg higher bits 33 Table 75: CRCResultReg register (address 22h); reset value: FFh . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 76: Description of CRCResultReg lower bits . 33 Table 77: Reserved register (address 23h); reset value: 88h. . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 78: Description of Reserved register bits . . . . 34 Table 79: ModWidthReg register (address 24h); reset value: 26h. . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 80: Description of ModWidthReg bits . . . . . . . 34 Table 81: Reserved register (address 25h); reset value: 87h. . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 82: Description of Reserved register bits . . . . 34 Table 83: RFCfgReg register (address 26h); reset value: 48h. . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 84: Description of RFCfgReg bits . . . . . . . . . . 35 Table 85: GsNReg register (address 27h); reset value: 88h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 86: Description of GsNOnReg bits . . . . . . . . . 35 Table 87: CWGsPReg register (address 28h); reset value: 20h. . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 88: Description of CWGsPReg bits . . . . . . . . 36 Table 89: ModGsPReg register (address 29h); reset value: 20h. . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 90: Description of ModGsPReg bits . . . . . . . . 36 Table 91: TModeReg register (address 2Ah); reset value: 00h. . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 92: Description of TModeReg bits . . . . . . . . . 37 Table 93: TPrescalerReg register (address 2Bh); reset value: 00h. . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 94: Description of TPrescalerReg bits . . . . . . 37 Table 95: TReloadReg (Higher bits) register (address 2Ch); reset value: 00h . . . . . . . . . . . . . . . 38 Table 96: Description of higher TReloadReg bits. . . 38 Table 97: TReloadReg (Lower bits)register (address 2Dh); reset value: 00h . . . . . . . . . . . . . . . 38 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 104 of 109 NXP Semiconductors MFRC522 Contactless Reader IC Table 174: Timing Specification for SPI. . . . . . . . . . 90 Table 175.Overview I2C Timing in Fast mode. . . . . 91 Table 176:Abbreviations . . . . . . . . . . . . . . . . . . . . . 97 Table 177:Revision history . . . . . . . . . . . . . . . . . . . 98 Table 131: Reserved register (address 3Eh); reset value: 03h. . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 132:Description of Reserved register bits . . . 45 Table 133:Reserved register (address 3Fh); reset value: 00h. . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 134:Description of Reserved register bits . . . 45 Table 135:Connection Scheme for detecting the different Interface Types . . . . . . . . . . . . . . 46 Table 136:Byte Order for MOSI and MISO . . . . . . . 47 Table 137:Byte Order for MOSI and MISO . . . . . . . 48 Table 138.Address byte 0 register; address MOSI . 48 Table 139:Settings of BR_T0 and BR_T1 . . . . . . . . 49 Table 140:Selectable transfer speeds . . . . . . . . . . . 49 Table 141:UART Framing . . . . . . . . . . . . . . . . . . . . 50 Table 142:Byte Order to Read Data . . . . . . . . . . . . 50 Table 143:Byte Order to Write Data. . . . . . . . . . . . . 51 Table 144.Address byte 0 register; address MOSI . 51 Table 145:Settings for TX1 . . . . . . . . . . . . . . . . . . . 61 Table 146:Settings for TX2 . . . . . . . . . . . . . . . . . . . 62 Table 147:CRC co-processor parameters . . . . . . . . 64 Table 148:Interrupt Sources . . . . . . . . . . . . . . . . . . 68 Table 149:Command overview . . . . . . . . . . . . . . . . 72 Table 150:TestSel2Reg register (address 07h) . . . . 76 Table 151:Description of Testsignals . . . . . . . . . . . . 77 Table 152:TestSel2Reg register (address 0Dh). . . . 77 Table 153:Description of Testsignals . . . . . . . . . . . . 77 Table 154:Testsignals description . . . . . . . . . . . . . . 77 Table 155.Limiting values . . . . . . . . . . . . . . . . . . . . 83 Table 156:Operating conditions . . . . . . . . . . . . . . . 83 Table 157:Thermal characteristics . . . . . . . . . . . . . 83 Table 158:Input Pin characteristics for pins EA, I2C and NRESET . . . . . . . . . . . . . . . . . . . . . . 84 Table 159:Input Pin characteristics for MFIN. . . . . . 84 Table 160:Input/Output Pin characteristics for pins D1, D2, D3, D4, D5, D6 and D7 . . . . . . . . . . . 84 Table 161:Input Pin characteristics for pin SDA . . . 84 Table 162:Output Pin characteristics for Pin MFOUT . 85 Table 163: Output Pin characteristics for Pin IRQ . . 85 Table 164: Input Pin characteristics for Pin Rx . . . . 85 Table 165:Input Pin characteristics for OSCIN . . . . 85 Table 166: Output Pin characteristics for Pins AUX1 and AUX2 . . . . . . . . . . . . . . . . . . . . . . . . . 86 Table 167: Output Pin characteristics for Pins TX1 and TX2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Table 168: Current Consumption. . . . . . . . . . . . . . . 87 Table 169: RX Input Voltage Range . . . . . . . . . . . . 88 Table 170: RX Input Sensitivity . . . . . . . . . . . . . . . . 88 Table 171: Clock Frequency . . . . . . . . . . . . . . . . . . 88 Table 172: XTAL Oscillator . . . . . . . . . . . . . . . . . . . 89 Table 173: XTAL Oscillator . . . . . . . . . . . . . . . . . . . 89 continued >> 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 105 of 109 NXP Semiconductors MFRC522 Contactless Reader IC 34. Figures Fig 1. Simplified MFRC522 Block diagram . . . . . . . 5 Fig 2. MFRC522 Block diagram . . . . . . . . . . . . . . . 6 Fig 3. Pinning configuration HVQFN32 (SOT617-1). 7 Fig 4. MFRC522 Reader/Writer mode. . . . . . . . . . . 9 Fig 5. ISO/IEC 14443A/MIFARE(R) Reader/Writer mode communication diagram. . . . . . . . . . . . 9 Fig 6. Data Coding and framing according to ISO/IEC 14443A.. . . . . . . . . . . . . . . . . . . . . 10 Fig 7. Connection to host with SPI . . . . . . . . . . . . 47 Fig 8. Connection to m-Controllers with UART.. . . 48 Fig 9. Schematic Diagram to Read Data. . . . . . . . 50 Fig 10. Schematic Diagram to Write Data. . . . . . . . 51 Fig 11. I2C interface. . . . . . . . . . . . . . . . . . . . . . . . . 52 Fig 12. Bit transfer on the I2C-bus. . . . . . . . . . . . . . 53 Fig 13. START and STOP conditions. . . . . . . . . . . . 53 Fig 14. Acknowledge on the I2C- bus. . . . . . . . . . . 54 Fig 15. Data transfer on the I2C- bus. . . . . . . . . . . . 55 Fig 16. First byte following the START procedure. . 56 Fig 17. Register Read and Write Access . . . . . . . . 57 Fig 18. I2C HS mode protocol switch . . . . . . . . . . . 58 Fig 19. I2C HS mode protocol frame. . . . . . . . . . . . 59 Fig 20. Serial data switch for TX1 and TX2. . . . . . . 63 Fig 21. Overview MFIN/MFOUT Signal Routing . . . 64 Fig 22. Ouartz Connection . . . . . . . . . . . . . . . . . . . 69 Fig 23. Oscillator Startup time. . . . . . . . . . . . . . . . . 71 Fig 24. Output TestDAC 1 on AUX1 and TestDAC 2 on AUX2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Fig 25. Output Testsignal Corr1 on AUX1 and MinLevel on AUX2. . . . . . . . . . . . . . . . . . . . 80 Fig 26. Output ADC channel I on AUX 1 and ADC channel Q on AUX 2. . . . . . . . . . . . . . . . . . 80 Fig 27. Output RxActive on AUX 1 and TxActive on AUX 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Fig 28. Output Rx data stream on AUX 1 and AUX 2. 82 Fig 29. RX Input Voltage Range . . . . . . . . . . . . . . . 88 Fig 30. Timing Diagram for SPI. . . . . . . . . . . . . . . . 90 Fig 31. Timing for F/S mode devices on the I2C-bus. . 91 Fig 32. Typical Application Circuit Diagram. . . . . . . 92 Fig 33. Package outline package version (HVQFN32) 93 Fig 34. Packing Information 1 Tray . . . . . . . . . . . . . 95 Fig 35. Packing Information 5Tray . . . . . . . . . . . . . 96 continued >> 112132 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 -- 22 May 2007 106 of 109 NXP Semiconductors MFRC522 Contactless Reader IC 35. Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 General description . . . . . . . . . . . . . . . . . . . 1 3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 Quick reference data . . . . . . . . . . . . . . . . . . 3 5 Ordering information . . . . . . . . . . . . . . . . . . 4 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . 5 7 Pinning information . . . . . . . . . . . . . . . . . . . 7 7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 7.2 Pin description. . . . . . . . . . . . . . . . . . . . . . . 7 8 Functional description . . . . . . . . . . . . . . . . . 9 9 MFRC522 Register SET . . . . . . . . . . . . . . 11 9.1 MFRC522 Registers Overview . . . . . . . . . 11 9.1.1 Register Bit Behavior . . . . . . . . . . . . . . . . 13 9.2 Register Description . . . . . . . . . . . . . . . . . 13 9.2.1 Page 0: Command and Status . . . . . . . . . 13 9.2.1.1 Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . 13 9.2.1.2 CommandReg . . . . . . . . . . . . . . . . . . . . . . 13 9.2.1.3 CommIEnReg . . . . . . . . . . . . . . . . . . . . . . 14 9.2.1.4 DivIEnReg . . . . . . . . . . . . . . . . . . . . . . . . . 16 9.2.1.5 CommIRqReg . . . . . . . . . . . . . . . . . . . . . . 16 9.2.1.6 DivIRqReg . . . . . . . . . . . . . . . . . . . . . . . . . 17 9.2.1.7 ErrorReg . . . . . . . . . . . . . . . . . . . . . . . . . . 18 9.2.1.8 Status1Reg . . . . . . . . . . . . . . . . . . . . . . . . 19 9.2.1.9 Status2Reg . . . . . . . . . . . . . . . . . . . . . . . . 20 9.2.1.10FIFODataReg . . . . . . . . . . . . . . . . . . . . . . 21 9.2.1.11FIFOLevelReg . . . . . . . . . . . . . . . . . . . . . 21 9.2.1.12WaterLevelReg . . . . . . . . . . . . . . . . . . . . . 21 9.2.1.13ControlReg . . . . . . . . . . . . . . . . . . . . . . . . 22 9.2.1.14BitFramingReg . . . . . . . . . . . . . . . . . . . . . 23 9.2.1.15CollReg. . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9.2.1.16Reserved . . . . . . . . . . . . . . . . . . . . . . . . . 24 9.2.2 Page 1: Communication . . . . . . . . . . . . . . 24 9.2.2.1 Reserved . . . . . . . . . . . . . . . . . . . . . . . . . 24 9.2.2.2 ModeReg. . . . . . . . . . . . . . . . . . . . . . . . . . 25 9.2.2.3 TxModeReg. . . . . . . . . . . . . . . . . . . . . . . . 25 9.2.2.4 RxModeReg . . . . . . . . . . . . . . . . . . . . . . . 26 9.2.2.5 TxControlReg . . . . . . . . . . . . . . . . . . . . . . 27 9.2.2.6 TxASKReg . . . . . . . . . . . . . . . . . . . . . . . . 28 9.2.2.7 TxSelReg . . . . . . . . . . . . . . . . . . . . . . . . . 28 9.2.2.8 RxSelReg . . . . . . . . . . . . . . . . . . . . . . . . . 29 9.2.2.9 RxThresholdReg . . . . . . . . . . . . . . . . . . . . 30 9.2.2.10DemodReg . . . . . . . . . . . . . . . . . . . . . . . . 9.2.2.11Reserved . . . . . . . . . . . . . . . . . . . . . . . . . 9.2.2.12Reserved . . . . . . . . . . . . . . . . . . . . . . . . . 9.2.2.13MfTxReg. . . . . . . . . . . . . . . . . . . . . . . . . . 9.2.2.14MfRxReg . . . . . . . . . . . . . . . . . . . . . . . . . 9.2.2.15Reserved . . . . . . . . . . . . . . . . . . . . . . . . . 9.2.2.16SerialSpeedReg . . . . . . . . . . . . . . . . . . . . 9.2.3 Page 2: Configuration . . . . . . . . . . . . . . . . 9.2.3.1 Reserved. . . . . . . . . . . . . . . . . . . . . . . . . . 9.2.3.2 CRCResultReg . . . . . . . . . . . . . . . . . . . . . 9.2.3.3 Reserved. . . . . . . . . . . . . . . . . . . . . . . . . . 9.2.3.4 ModWidthReg . . . . . . . . . . . . . . . . . . . . . . 9.2.3.5 Reserved. . . . . . . . . . . . . . . . . . . . . . . . . . 9.2.3.6 RFCfgReg . . . . . . . . . . . . . . . . . . . . . . . . . 9.2.3.7 GsNReg . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2.3.8 CWGsPReg . . . . . . . . . . . . . . . . . . . . . . . 9.2.3.9 ModGsPReg . . . . . . . . . . . . . . . . . . . . . . . 9.2.3.10TMode Register, TPrescaler Register . . . 9.2.3.11TReloadReg . . . . . . . . . . . . . . . . . . . . . . . 9.2.3.12TCounterValReg. . . . . . . . . . . . . . . . . . . . 9.2.4 Page 3: Test . . . . . . . . . . . . . . . . . . . . . . . 9.2.4.1 Reserved. . . . . . . . . . . . . . . . . . . . . . . . . . 9.2.4.2 TestSel1Reg . . . . . . . . . . . . . . . . . . . . . . . 9.2.4.3 TestSel2Reg . . . . . . . . . . . . . . . . . . . . . . . 9.2.4.4 TestPinEnReg . . . . . . . . . . . . . . . . . . . . . . 9.2.4.5 TestPinValueReg. . . . . . . . . . . . . . . . . . . . 9.2.4.6 TestBusReg. . . . . . . . . . . . . . . . . . . . . . . . 9.2.4.7 AutoTestReg . . . . . . . . . . . . . . . . . . . . . . . 9.2.4.8 VersionReg . . . . . . . . . . . . . . . . . . . . . . . . 9.2.4.9 AnalogTestReg . . . . . . . . . . . . . . . . . . . . . 9.2.4.10TestDAC1Reg . . . . . . . . . . . . . . . . . . . . . 9.2.4.11TestDAC2Reg. . . . . . . . . . . . . . . . . . . . . . 9.2.4.12TestADCReg . . . . . . . . . . . . . . . . . . . . . . 9.2.4.13Reserved . . . . . . . . . . . . . . . . . . . . . . . . . 10 DIGITAL Interfaces . . . . . . . . . . . . . . . . . . 10.1 Automatic m-Controller Interface Type Detection. . . . . . . . . . . . . . . . . . . . . . . . . . 10.2 SPI Compatible interface . . . . . . . . . . . . . 10.2.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.2 Read data . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.3 Write data . . . . . . . . . . . . . . . . . . . . . . . . . 30 31 31 31 32 32 32 33 33 33 34 34 34 35 35 36 36 37 38 39 39 39 40 40 41 41 42 42 42 43 44 44 44 45 46 46 46 47 47 48 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'. (c) NXP B.V. 2007. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: sales.addresses@www.nxp.com Date of release: 22 May 2007 Document identifier: 112132 NXP Semiconductors MFRC522 Contactless Reader IC 18.2 General Behavior . . . . . . . . . . . . . . . . . . . 72 18.3 MFRC522 Commands Overview . . . . . . . 72 18.3.1 MFRC522 Command Description . . . . . . . 73 18.3.1.1Idle Command . . . . . . . . . . . . . . . . . . . . . 73 18.3.1.2Mem Command . . . . . . . . . . . . . . . . . . . . 73 18.3.1.3Generate RandomID Command . . . . . . . 73 18.3.1.4CalcCRC Command. . . . . . . . . . . . . . . . . 73 18.3.1.5Transmit Command . . . . . . . . . . . . . . . . . 73 18.3.1.6NoCmdChange Command . . . . . . . . . . . 73 18.3.1.7Receive Command. . . . . . . . . . . . . . . . . . 74 18.3.1.8Transceive Command . . . . . . . . . . . . . . . 74 18.3.1.9MFAuthent Command . . . . . . . . . . . . . . . 74 18.3.1.10SoftReset Command . . . . . . . . . . . . . . . 75 19 Testsignals . . . . . . . . . . . . . . . . . . . . . . . . 76 19.1 Selftest . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 19.2 Test bus. . . . . . . . . . . . . . . . . . . . . . . . . . . 76 19.3 Testsignals at pin AUX . . . . . . . . . . . . . . . 77 19.3.1 Example: Output TestDAC 1 on AUX1 and TestDAC 2 on AUX2 . . . . . . . . . . . . . . . . . 79 19.3.2 Example: Output Testsignal Corr1 on AUX1 and MinLevel on AUX2 . . . . . . . . . . . . . . . 79 19.3.3 Example: Output ADC channel I on AUX 1 and ADC channel Q on AUX 2. . . . . . . . . . . . . 80 19.3.4 Example: Output RxActive on AUX 1 and TxActive on AUX 2 . . . . . . . . . . . . . . . . . . 81 19.3.5 Example: Output Rx Data Stream on AUX 1 and AUX 2. . . . . . . . . . . . . . . . . . . . . . . . . 82 19.4 PRBS (Pseudo-Random Binary Sequence) 82 20 Limiting values . . . . . . . . . . . . . . . . . . . . . 83 21 Recommended operating conditions . . . . 83 22 Thermal characteristics. . . . . . . . . . . . . . . 83 23 Characteristics . . . . . . . . . . . . . . . . . . . . . 84 23.1 Input Pin Characteristics . . . . . . . . . . . . . . 84 23.1.1 Input Pin characteristics for pins EA, I2C and NRESET . . . . . . . . . . . . . . . . . . . . . . . . . . 84 23.1.2 Input Pin characteristics for pin MFIN . . . . 84 23.1.3 Input/Output Pin characteristics for pins D1, D2, D3, D4, D5, D6 and D7 . . . . . . . . . . . 84 23.1.4 Input Pin characteristics for pin SDA . . . . 84 23.1.5 Output Pin characteristics for Pin MFOUT 85 23.1.6 Output Pin characteristics for Pin IRQ . . . 85 23.1.7 Input Pin characteristics for Pin Rx . . . . . . 85 23.1.8 Input Pin characteristics for pin OSCIN . . 85 10.2.4 Address byte . . . . . . . . . . . . . . . . . . . . . . . 48 10.3 UART Interface . . . . . . . . . . . . . . . . . . . . . 48 10.3.1 Connection to a host . . . . . . . . . . . . . . . . . 48 10.3.2 Selection of the transfer speeds . . . . . . . . 49 10.3.3 Framing . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 10.4 I2C Bus Interface . . . . . . . . . . . . . . . . . . . 52 10.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 10.4.2 Data validity. . . . . . . . . . . . . . . . . . . . . . . . 53 10.4.3 START and STOP conditions . . . . . . . . . . 53 10.4.4 Byte format . . . . . . . . . . . . . . . . . . . . . . . . 54 10.4.5 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . 54 10.4.6 7-BIT ADDRESSING. . . . . . . . . . . . . . . . . 55 10.4.7 Register Write Access . . . . . . . . . . . . . . . 56 10.4.8 Register Read Access. . . . . . . . . . . . . . . . 57 10.4.9 HS mode . . . . . . . . . . . . . . . . . . . . . . . . . 58 10.4.10High Speed Transfer . . . . . . . . . . . . . . . . . 58 10.4.11 Serial Data transfer Format in HS mode . . 58 10.4.12Switching from F/S to HS mode and Vice Versa 60 10.4.13MFRC522 at Lower Speed modes . . . . . . 60 11 Analog Interface and Contactless UART. . 61 11.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 11.2 TX Driver . . . . . . . . . . . . . . . . . . . . . . . . . 61 11.3 Serial Data Switch . . . . . . . . . . . . . . . . . . 63 11.4 MFIN/MFOUT interface support . . . . . . . . 63 11.5 CRC co-processor. . . . . . . . . . . . . . . . . . . 64 12 FIFO Buffer . . . . . . . . . . . . . . . . . . . . . . . . 65 12.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . 65 12.2 Accessing the FIFO Buffer . . . . . . . . . . . . 65 12.3 Controlling the FIFO-Buffer . . . . . . . . . . . . 65 12.4 Status Information about the FIFO-Buffer . 65 13 Timer Unit . . . . . . . . . . . . . . . . . . . . . . . . . 67 14 Interrupt Request System . . . . . . . . . . . . . 68 15 Oscillator Circuitry . . . . . . . . . . . . . . . . . . . 69 16 Power Reduction modes . . . . . . . . . . . . . . 70 16.1 Hard Power-down . . . . . . . . . . . . . . . . . . . 70 16.2 Soft Power-down . . . . . . . . . . . . . . . . . . . . 70 16.3 Transmitter Power-down . . . . . . . . . . . . . . 70 17 Reset and Oscillator Startup Time . . . . . . 71 17.1 Reset Timing Requirements . . . . . . . . . . . 71 17.2 Oscillator Startup Time . . . . . . . . . . . . . . . 71 18 MFRC522 Command Set . . . . . . . . . . . . . 72 18.1 General Description . . . . . . . . . . . . . . . . . 72 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'. (c) NXP B.V. 2007. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: sales.addresses@www.nxp.com Date of release: 22 May 2007 Document identifier: 112132 NXP Semiconductors MFRC522 Contactless Reader IC 23.1.9 Output Pin characteristics for Pins AUX1 and AUX2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 23.1.10Output Pin characteristics for Pins TX1 and TX2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 23.2 Current Consumption . . . . . . . . . . . . . . . . 87 23.3 RX Input Voltage Range . . . . . . . . . . . . . . 88 23.4 RX Input Sensitivity . . . . . . . . . . . . . . . . . . 88 23.5 Clock Frequency . . . . . . . . . . . . . . . . . . . . 88 23.6 XTAL Oscillator . . . . . . . . . . . . . . . . . . . . . 89 23.7 Typical 27.12 MHz Crystal Requirements . 89 23.8 Timing for the SPI compatible interface . . 90 23.9 I2C Timing . . . . . . . . . . . . . . . . . . . . . . . . . 91 24 Application information . . . . . . . . . . . . . . . 92 25 Package outline. . . . . . . . . . . . . . . . . . . . . 93 26 Handling information . . . . . . . . . . . . . . . . . 94 27 Packing information. . . . . . . . . . . . . . . . . . 95 28 Abbreviations . . . . . . . . . . . . . . . . . . . . . . 97 29 References . . . . . . . . . . . . . . . . . . . . . . . . 97 30 Revision history . . . . . . . . . . . . . . . . . . . . . 98 31 Legal information. . . . . . . . . . . . . . . . . . . 100 31.1 Data sheet status . . . . . . . . . . . . . . . . . . 100 31.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . 100 31.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . 100 31.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . 100 32 Contact information . . . . . . . . . . . . . . . . . 101 33 Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 34 Figures . . . . . . . . . . . . . . . . . . . . . . . . . . 106 35 Contents . . . . . . . . . . . . . . . . . . . . . . . . . 107 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'. (c) NXP B.V. 2007. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: sales.addresses@www.nxp.com Date of release: 22 May 2007 Document identifier: 112132 |
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